5.5 A 2.1e- Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology. - Jaekyu Lee; Seung Sik Kim; In-Gyu Baek; Heesung Shim; Taehoon Kim; Taehyoung Kim; Jungchan Kyoung; Dongmo Im; Jinyong Choi; KeunYeong Cho; Daehoon Kim; Haemin Lim; et al. (ISSCC, 2020)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

6.10 A 1/1.56-inch 50Mpixel CMOS Image Sensor with 0.5μm pitch Quad Photodiode Separated by Front Deep Trench Isolation. - DongHyun Kim; Kwansik Cho; Ho-Chul Ji; Minkyung Kim 010; Junghye Kim; Taehoon Kim; Seungju Seo; Dongmo Im; You-Na Lee 001; Jinyong Choi; Sunghyun Yoon; Inho Noh; et al. (ISSCC, 2024)