12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. - Giyoung Yang; Hakchul Jung; Jinyoung Lim; Jaewoo Seo; Ingyum Kim; Jisu Yu; Hyeoungyu You; Jeongsoon Kong; Garoom Kim; Minjae Jeong; Chanhee Park; Sera An; et al. (VLSI Technology and Circuits, 2022)

Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA. - Seungyoung Lee; Sungyup Jung; Yunkyeong Jang; Jungho Do; Jisu Yu; Hyeoungyu You; Minjae Jeong; Jinyoung Lim; Jiyun Han; Sangdo Park; Yongdeok Kim; Jooyeon Kwon; et al. (VLSI Technology and Circuits, 2023)