Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (ICCAD, 2000)

Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (DAC, 2001)

Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. - Jiong Luo; Niraj K. Jha (HiPC, 2002)

Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. - Lin Zhong 001; Jiong Luo; Yunsi Fei; Niraj K. Jha (ICCD, 2002)

Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. - Jiong Luo; Niraj K. Jha (ASP-DAC/VLSI Design, 2002)

A comprehensive high-level synthesis system for control-flow intensive behaviors. - Weidong Wang; Tat Kee Tan; Jiong Luo; Yunsi Fei; Li Shang; Keith S. Vallerio; Lin Zhong 001; Anand Raghunathan; Niraj K. Jha (ACM Great Lakes Symposium on VLSI, 2003)

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. - Le Yan; Jiong Luo; Niraj K. Jha (ICCAD, 2003)

Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. - Jiong Luo; Niraj K. Jha (VLSI Design, 2003)

Register binding-based RTL power management for control-flow intensive designs. - Jiong Luo; Lin Zhong 001; Yunsi Fei; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. - Le Yan; Jiong Luo; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. - Jiong Luo; Niraj K. Jha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. - Jiong Luo; Niraj K. Jha; Li-Shiuan Peh (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Multi-level logic benchmarks: An exactness study. - Luca Gaetano Amarù; Mathias Soeken; Winston Haaswijk; Eleonora Testa; Patrick Vuillod; Jiong Luo; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (ASP-DAC, 2017)

Logic optimization and synthesis: Trends and directions in industry. - Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Janet Olson (DATE, 2017)

Enabling exact delay synthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon; Janet Olson; Robert K. Brayton; Giovanni De Micheli (ICCAD, 2017)

Improvements to boolean resynthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Janet Olson; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Integrated ESOP Refactoring for Industrial Designs. - Winston Haaswijk; Luca Gaetano Amarù; Patrick Vuillod; Jiong Luo; Mathias Soeken; Giovanni De Micheli (ICECS, 2018)

Scalable Boolean Methods in a Modern Synthesis Flow. - Eleonora Testa; Luca G. Amarù; Mathias Soeken; Alan Mishchenko; Patrick Vuillod; Jiong Luo; Christopher Casares; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (DATE, 2019)

SAT-Sweeping Enhanced for Logic Synthesis. - Luca G. Amarù; Felipe S. Marranghello; Eleonora Testa; Christopher Casares; Vinicius N. Possani; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2020)

LUT-Based Optimization For ASIC Design Flow. - Luca Gaetano Amarù; Vinicius N. Possani; Eleonora Testa; Felipe S. Marranghello; Christopher Casares; Jiong Luo; Patrick Vuillod; Alan Mishchenko; Giovanni De Micheli (DAC, 2021)

Improving LUT-based optimization for ASICs. - Walter Lau Neto; Luca G. Amarù; Vinicius Possani; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon (DAC, 2022)

IMH-MOT: Interactive Multi-Hierarchical Image and Point Cloud Fusion for Multi-Object Tracking. - Wenyuan Qin; Zhiyan Zhou; Jiong Luo; Chengwei Pan; Hao Xu 032; Xiwang Dong; Danwei Wang (IEEE Robotics Autom. Lett., 2025)