Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (PCS, 2022)

Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (IEEE Des. Test, 2022)

Analysis of AV1 Arithmetic Decoder Design Space with a Novel Multi-Boolean Approach. - Jiovana Sousa Gomes; Tulio Pereira Bitencourt; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2023)

AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture. - Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Fábio Luís Livi Ramos; Sergio Bampi (SBCCI, 2023)

Statistical Analysis of VVC Residual and Entropy Coding aiming Efficient Hardware Design. - Gabriel Bitencourt Cardoso; Daniel Felipe Tomm; Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2024)

High-Performance Binary Arithmetic Encoder with Multiple Bypass Bin Scheme for VVC CABAC. - Vinícius Martins Faria; Jiovana Sousa Gomes; Sergio Bampi; Fábio Luís Livi Ramos (LASCAS, 2025)

End-to-End Neural Video Compression: A Review. - Jiovana Sousa Gomes; Mateus Grellert; Fábio Luís Livi Ramos; Sergio Bampi (IEEE Open J. Circuits Syst., 2025)

Hardware accelerator for VVC/H.266 residual syntax elements: a unified and resource-efficient architecture. - Gabriel Bitencourt Cardoso; Heitor Mauro Chavez Huarachi; Daniel Felipe Tomm; Jiovana Sousa Gomes; Rodrigo N. Wuerdig; Marcelo Romero de Moraes; Sergio Bampi; Fábio Luís Livi Ramos (J. Real Time Image Process., 2025)