IDDT ATPG Based on Ambiguous Delay Assignments. - Jishun Kuang; Yu Wang; Xiaofen Wei; Changnian Zhang (Asian Test Symposium, 2003)

At-Speed Current Testing. - Yinghua Min; Jishun Kuang; Xiaoyan Niu (Asian Test Symposium, 2003)

IDDT: Fundamentals and Test Generation. - Jishun Kuang; Zhiqiang Yang; Qijian Zhu; Yinghua Min (J. Comput. Sci. Technol., 2003)

A New BIST Solution for System-on-Chip. - Ling Zhang; Jishun Kuang (PRDC, 2005)

DCScan: A Power-Aware Scan Testing Architecture. - Gui Dai; Zhiqiang You; Jishun Kuang; Jiedi Huang (ATS, 2008)

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself. - Jishun Kuang; Ouyang Xiong; Zhiqiang You (ATS, 2008)

Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. - Yong-sheng Cheng; Zhiqiang You; Jishun Kuang (DELTA, 2008)

Small Delay Fault Simulation for Sequential Circuits. - Li Liu; Jishun Kuang; Huawei Li 001 (PRDC, 2009)

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. - Zhiqiang You; Jiedi Huang; Michiko Inoue; Jishun Kuang; Hideo Fujiwara (Asian Test Symposium, 2010)

Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core. - Ling Zhang; Jishun Kuang; Zhiqiang You (ICA3PP (2), 2010)

Test Data Compression Using Selective Sparse Storage. - Ling Zhang; Jishun Kuang; Zhiqiang You (J. Electron. Test., 2011)

A scan disabling-based BAST scheme for test cost reduction. - Zhiqiang You; Weizheng Wang 002; Zhiping Dou; Peng Liu 045; Jishun Kuang (IEICE Electron. Express, 2011)

A New Test Data Compression Scheme. - Ling Zhang; Jishun Kuang (J. Comput., 2011)

Test data compression using interval broadcast scan for embedded cores. - Ling Zhang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2011)

Switching activity reduction for scan-based BIST using weighted scan input data. - Weizheng Wang 002; Jishun Kuang; Peng Liu 045; Xin Peng; Zhiqiang You (IEICE Electron. Express, 2012)

A scan disabling-based BAST scheme for test cost and test power reduction. - Zhiqiang You; Weizheng Wang 002; Peng Liu 045; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2012)

Virtual scan chains reordering using a RAM-based module for high test compression. - Ling Zhang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2012)

Achieving low capture and shift power in linear decompressor-based test compression environment. - Weizheng Wang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2012)

Comparator and half adder design using complementary resistive switches crossbar. - Bosheng Liu; Zhiqiang You; Xiangrao Li; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2013)

An adaptive neural network A/D converter based on CMOS/memristor hybrid design. - Weiwei Wang; Zhiqiang You; Peng Liu; Jishun Kuang (IEICE Electron. Express, 2014)

Improve the compression ratios for code-based test vector compressions by decomposing. - Jishun Kuang; Liang Zhang; Zhiqiang You; Yingbo Zhou (ETS, 2015)

An active rectifier with optimal flip timing for the internal capacitor for piezoelectric vibration energy harvesting. - Liao Wu; Dong Sam Ha; Jishun Kuang; Xuan-Dien Do; Sang-Gug Lee 001 (MWSCAS, 2015)

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. - Peng Liu 045; Zhiqiang You; Jishun Kuang; Zhipeng Hu; Weizheng Wang 002 (IEICE Electron. Express, 2015)

An efficient small-delay faults simulator based on critical path tracing. - Tieqiao Liu; Jishun Kuang; Shuo Cai; Zhiqiang You (Int. J. Circuit Theory Appl., 2015)

A sort method to enhance significant spectral components of test set. - Yingbo Zhou; Jishun Kuang (ICNC-FSKD, 2016)

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting. - Liao Wu; Jishun Kuang; Zhiqiang You; Peng Liu 045; Shuo Cai (IEICE Electron. Express, 2016)

Representative Scan Architecture. - Ling Zhang; Jishun Kuang (J. Circuits Syst. Comput., 2016)

A novel memristor-based restricted Boltzmann machine for contrastive divergence. - Yan Chen; Zhiqiang You; Yingjie Zhang; Jishun Kuang; Jing Zhang (IEICE Electron. Express, 2018)

Design and Implementation of GPU Accelerated Active Storage in FastDFS. - Zaihong He; Jishun Kuang; Yanjie Tan; Wenjie Liu; Bin Sheng (HPCC/SmartCity/DSS, 2019)

A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data. - Minghe Zhang; Jishun Kuang; Jing Huang; Zhiqiang You (HPCC/SmartCity/DSS, 2019)

LPCMsim: A Lightweight Phase Change Memory Simulator. - Zaihong He; Jishun Kuang; Yanjie Tan; Shihui Peng; Huailiang Tan (Future Gener. Comput. Syst., 2019)

Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms. - Minghe Zhang; Jishun Kuang; Jing Huang 012; Renfa Li (J. Circuits Syst. Comput., 2021)

Small-Signal Processing Low-Overhead Operational Amplifier for delta-Sigma ADC. - Jinhui Tan; Jishun Kuang; Xing Hu; Lin Xiao (J. Circuits Syst. Comput., 2022)

The design of ΔΣ-ADC in MEMS gyro interface ASIC. - Jinhui Tan; Jishun Kuang; Xing Hu; Xiaomin Cai; Jiahe Shi (Microelectron. J., 2023)