Exploring eFPGA-based Redaction for IP Protection. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (ICCAD, 2021)

Security Closure of Physical Layouts ICCAD Special Session Paper. - Johann Knechtel; Jayanth Gopinath; Jitendra Bhandari; Mohammed Ashraf; Hussam Amrouch; Shekhar Borkar; Sung Kyu Lim; Ozgur Sinanoglu; Ramesh Karri (ICCAD, 2021)

ALICE: an automatic design flow for eFPGA redaction. - Chiara Muscari Tomajoli; Luca Collini; Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (DAC, 2022)

Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. - Johann Knechtel; Jayanth Gopinath; Mohammed Ashraf; Jitendra Bhandari; Ozgur Sinanoglu; Ramesh Karri (ISPD, 2022)

ConVERTS: Contrastively Learning Structurally InVariant Netlist Representations. - Animesh Basak Chowdhury; Jitendra Bhandari; Luca Collini; Ramesh Karri; Benjamin Tan 001; Siddharth Garg (MLCAD, 2023)

DEFending Integrated Circuit Layouts. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ramesh Karri (IACR Cryptol. ePrint Arch., 2023)

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. - Jitendra Bhandari; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Christian Pilato; Ganesh Gore; Xifan Tang; Scott Temple; Pierre-Emmanuel Gaillardon; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (APCCAS, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (ICCAD, 2024)

Lightweight Masking Against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Thari Nabeel; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (CoRR, 2024)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines. - Jitendra Bhandari; Johann Knechtel; Ramesh Narayanaswamy; Siddharth Garg; Ramesh Karri (CoRR, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Mohammed Nabeel 001; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (CoRR, 2024)

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions. - Jitendra Bhandari; Rajat Sadhukhan; Prashanth Krishnamurthy; Farshad Khorrami; Ramesh Karri (CoRR, 2024)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI. - Jitendra Bhandari; Vineet Bhat; Yuheng He; Siddharth Garg; Hamed Rahmani; Ramesh Karri (CoRR, 2024)

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. - Jitendra Bhandari; Likhitha Mankali; Mohammed Nabeel 001; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. - Lakshmi Likhitha Mankali; Jitendra Bhandari; Manaar Alam; Ramesh Karri; Michail Maniatakos; Ozgur Sinanoglu; Johann Knechtel (DATE, 2025)

LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Nabeel 001; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (ISCAS, 2025)

DEFending Integrated Circuit Layouts. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Inf. Forensics Secur., 2025)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding. - Zeng Wang; Minghao Shao; Mohammed Nabeel 001; Prithwish Basu Roy; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammed Shafique 001; Johann Knechtel (CoRR, 2025)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination. - Zeng Wang; Minghao Shao; Jitendra Bhandari; Likhitha Mankali; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Khader Thalakkattu Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (CoRR, 2025)

SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design. - Zeng Wang; Minghao Shao; Rupesh Raj Karn; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. - Raghu Vamshi Hemadri; Jitendra Bhandari; Andre Nakkab; Johann Knechtel; Badri P. Gopalan; Ramesh Narayanaswamy; Ramesh Karri; Siddharth Garg (CoRR, 2025)

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction. - Luca Collini; Jitendra Bhandari; Chiara Muscari Tomajoli; Abdul Moosa; Benjamin Tan 001; Xifan Tang; Pierre-Emmanuel Gaillardon; Ramesh Karri; Christian Pilato (ACM Trans. Design Autom. Electr. Syst., 2025)