Design for testability view on placement and routing. - Derek B. I. Feltham; Jitendra Khare; Wojciech Maly (EURO-DAC, 1992)

Estimation of reject ratio in testing of combinatorial circuits. - Dinesh D. Gaitonde; Jitendra Khare; D. M. H. Walker; Wojciech P. Maly (VTS, 1993)

Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits. - Jitendra Khare; Derek B. I. Feltham; Wojciech Maly (IEEE J. Solid State Circuits, 1993)

Inductive Contamination Analysis (ICA) with SRAM Application. - Jitendra Khare; Wojciech Maly (ITC, 1995)

Testability-oriented channel routing. - Jitendra Khare; Sujoy Mitra; Pranab K. Nag; U. Maly; Rob A. Rutenbar (VLSI Design, 1995)

Design for manufacturability in submicron domain. - Wojciech Maly; Hans T. Heineken; Jitendra Khare; Pranab K. Nag (ICCAD, 1996)

Fault characterization of standard cell libraries using inductive contamination. - Jitendra Khare; Wojciech Maly; Nathan Tiday (VTS, 1996)

CAD at the Design-Manufacturing Interface. - Hans T. Heineken; Jitendra Khare; Wojciech Maly; Pranab K. Nag; Charles H. Ouyang; Witold A. Pleskacz (DAC, 1997)

Manufacturability analysis of standard cell libraries. - Hans T. Heineken; Jitendra Khare; Manuel d'Abreu (CICC, 1998)

Design-Manufacturing Interface: Part I - Vision. - Wojciech Maly; Pranab K. Nag; Hans T. Heineken; Jitendra Khare (DATE, 1998)

Design-Manufacturing Interface: Part II - Applications. - Wojciech Maly; Pranab K. Nag; Charles H. Ouyang; Hans T. Heineken; Jitendra Khare; P. Simon (DATE, 1998)

Cost Trade-Offs in System On Chip Designs. - Jitendra Khare; Hans T. Heineken; Manuel d'Abreu (VLSI Design, 2000)

Maximizing Wafer Productivity Through Layout Optimization. - Charles H. Ouyang; Hans T. Heineken; Jitendra Khare; Saghir A. Shaikh; Manuel d'Abreu (VLSI Design, 2000)

Manufacturability and Testability Oriented Synthesis. - Saghir A. Shaikh; Jitendra Khare; Hans T. Heineken (VLSI Design, 2000)

Test and Debug of Networking SoCs: A Case Study. - A. Bommireddy; Jitendra Khare; Saghir A. Shaikh; S.-T. Su (VTS, 2000)

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. - John T. Chen; Jitendra Khare; Ken Walker; Saghir A. Shaikh; Janusz Rajski; Wojciech Maly (ITC, 2001)

Enabling Embedded Memory Diagnosis via Test Response Compression. - John T. Chen; Wojciech Maly; Janusz Rajski; Omar Kebichi; Jitendra Khare (VTS, 2001)

DFM - A Fabless Perspective. - Jitendra Khare (ITC, 2003)

Test Strategies For a 40Gbps Framer SoC. - Hans T. Heineken; Jitendra Khare (ITC, 2004)

Memory Yield Improvement - SoC Design Perspective. - Jitendra Khare (ITC, 2004)

Embedded Memory Field Returns - Trials and Tribulations. - Jitendra Khare; Amit B. Shah; Ashok Raman; Girish Rayas (ITC, 2006)