GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

A general approach for identifying hierarchical symmetry constraints for analog circuit layout. - Kishor Kunal; Jitesh Poojary; Tonmoy Dhar; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. - Tonmoy Dhar; Jitesh Poojary; Yaguang Li; Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Susmita Dey Manasi; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (ASP-DAC, 2021)

Aging of Current DACs and its Impact in Equalizer Circuits. - Tonmoy Dhar; Jitesh Poojary; Ramesh Harjani; Sachin S. Sapatnekar (IRPS, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB. - Jitesh Poojary; Ramesh Harjani (ISSCC, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. - Tonmoy Dhar; Ramprasath S 001; Jitesh Poojary; Soner Yaldiz; Steven M. Burns; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. - Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Ramprasath S 001; Kishor Kunal; Sachin S. Sapatnekar; Ramesh Harjani (ESSDERC, 2023)

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

Reinforcing the Connection between Analog Design and EDA (Invited Paper). - Kishor Kunal; Meghna Madhusudan; Jitesh Poojary; S. Ramprasath 001; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. - Kishor Kunal; Jitesh Poojary; S. Ramprasath 001; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)