A New Receiver Architecture for MIMO Beam-Forming Applications. - Yucheng Dai; Yahia R. Ramadan; Hlaing Minn; Jiu Xiong; Jin Liu 004; Alan Gatherer (GLOBECOM, 2017)

An open-loop 28GHz 16-phase clock generator in 28nm CMOS. - Jiu Xiong; Jin Liu 004; Yucheng Dai; Hlaing Minn (MWSCAS, 2017)

High-Speed ADC Quantization with Overlapping Metastability Zones. - Jiajun Ren; Jiu Xiong; Jin Liu 004 (MWSCAS, 2018)

ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration. - Jiajun Ren; Jiu Xiong; Jin Liu 004 (MWSCAS, 2019)

An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC. - Jiu Xiong; Jiajun Ren; Jin Liu 004 (MWSCAS, 2019)

A 3rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators. - Jiu Xiong; Jeniffer Zhao; Jin Liu 004; Hoi Lee (ISCAS, 2022)

A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator. - Jiu Xiong; Jin Liu 004; Hoi Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)