Analog Fault Diagnosis for Unpowered Circuit Boards. - Jiun-Lang Huang; Kwang-Ting Cheng (ITC, 1997)

Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. - Jiun-Lang Huang; Chen-Yang Pan; Kwang-Ting Cheng (VTS, 1999)

A sigma-delta modulation based BIST scheme for mixed-signal circuits. - Jiun-Lang Huang; Kwang-Ting Cheng (ASP-DAC, 2000)

A BIST Scheme for On-Chip ADC and DAC Testing. - Jiun-Lang Huang; Chee-Kian Ong; Kwang-Ting Cheng (DATE, 2000)

Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis. - Jiun-Lang Huang; Kwang-Ting Cheng (ITC, 2000)

Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. - Jan Arild Tofte; Chee-Kian Ong; Jiun-Lang Huang; Kwang-Ting (Tim) Cheng (VTS, 2000)

An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. - Jiun-Lang Huang; Kwang-Ting Cheng (VTS, 2001)

On-chip Analog Response Extraction with 1-Bit ? - Modulators. - Hao-Chiao Hong; Jiun-Lang Huang; Kwang-Ting Cheng; Cheng-Wen Wu (Asian Test Symposium, 2002)

A Low-Cost Jitter Measurement Technique for BIST Applications. - Jui-Jer Huang; Jiun-Lang Huang (Asian Test Symposium, 2003)

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. - Hao-Chiao Hong; Jiun-Lang Huang; Kwang-Ting Cheng; Cheng-Wen Wu; Ding-Ming Kwai (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

An Infrastructure IP for On-Chip Clock Jitter Measurement. - Jui-Jer Huang; Jiun-Lang Huang (ICCD, 2004)

Random Jitter Testing Using Low Tap-Count Delay Lines. - Jiun-Lang Huang (Asian Test Symposium, 2005)

A routability constrained scan chain ordering technique for test power reduction. - Xuan-Lun Huang; Jiun-Lang Huang (ASP-DAC, 2006)

A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter. - Jiun-Lang Huang (ATS, 2006)

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. - Jiun-Lang Huang (J. Electron. Test., 2006)

A Low-Cost Jitter Measurement Technique for BIST Applications. - Jiun-Lang Huang; Jui-Jer Huang; Yuan-Shuang Liu (J. Electron. Test., 2006)

An Efficient Peak Power Reduction Technique for Scan Testing. - Meng-Fan Wu; Kai-Shun Hu; Jiun-Lang Huang (ATS, 2007)

Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry. - Jui-Jer Huang; Chiuan-Che Li; Jiun-Lang Huang (ATS, 2008)

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment. - Yi-Tsung Lin; Meng-Fan Wu; Jiun-Lang Huang (ATS, 2008)

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs. - Shianling Wu; Laung-Terng Wang; Zhigang Jiang; Jiayong Song; Boryau Sheu; Xiaoqing Wen; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Ravi Apte (DFT, 2008)

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing. - Meng-Fan Wu; Jiun-Lang Huang; Xiaoqing Wen; Kohei Miyase (ITC, 2008)

A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays. - Chen-Wei Lin; Jiun-Lang Huang (VTS, 2008)

Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input. - Xuan-Lun Huang; Chen-Yuan Yang; Jiun-Lang Huang (ASP-DAC, 2009)

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing. - Chen-Yuan Yang; Xuan-Lun Huang; Jiun-Lang Huang (Asian Test Symposium, 2009)

LPTest: a Flexible Low-Power Test Pattern Generator. - Meng-Fan Wu; Kai-Shun Hu; Jiun-Lang Huang (J. Electron. Test., 2009)

A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. - Chen-Wei Lin; Jiun-Lang Huang (J. Comput., 2009)

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment. - Meng-Fan Wu; Jiun-Lang Huang; Xiaoqing Wen; Kohei Miyase (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Improved weight assignment for logic switching activity during at-speed test pattern generation. - Meng-Fan Wu; Hsin-Cheih Pan; Teng-Han Wang; Jiun-Lang Huang; Kun-Han Tsai; Wu-Tung Cheng (ASP-DAC, 2010)

Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing. - Chun-Yong Liang; Meng-Fan Wu; Jiun-Lang Huang (Asian Test Symposium, 2010)

An error tolerance scheme for 3D CMOS imagers. - Hsiu-Ming Chang 001; Jiun-Lang Huang; Ding-Ming Kwai; Kwang-Ting (Tim) Cheng; Cheng-Wen Wu (DAC, 2010)

A robust ADC code hit counting technique. - Jiun-Lang Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang (DATE, 2010)

A scalable quantitative measure of IR-drop effects for scan pattern generation. - Meng-Fan Wu; Kun-Han Tsai; Wu-Tung Cheng; Hsin-Cheih Pan; Jiun-Lang Huang; Augusli Kifli (ICCAD, 2010)

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. - Xuan-Lun Huang; Jiun-Lang Huang (VTS, 2010)

CSER: BISER-based concurrent soft-error resilience. - Laung-Terng Wang; Nur A. Touba; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; James Chien-Mo Li (VTS, 2010)

A self-testing and calibration method for embedded successive approximation register ADC. - Xuan-Lun Huang; Ping-Ying Kang; Hsiu-Ming Chang 001; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai; Cheng-Wen Wu (ASP-DAC, 2011)

A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. - Xuan-Lun Huang; Ping-Ying Kang; Jiun-Lang Huang; Yung-Fa Chou; Yung-Pin Lee; Ding-Ming Kwai (ETS, 2011)

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. - Yi-Tsung Lin; Jiun-Lang Huang; Xiaoqing Wen (ITC, 2011)

A Promising Alternative to Conventional Silicon. - Jiun-Lang Huang; Kwang-Ting (Tim) Cheng (IEEE Des. Test Comput., 2011)

Robust Circuit Design for Flexible Electronics. - Tsung-Ching Huang; Jiun-Lang Huang; Kwang-Ting (Tim) Cheng (IEEE Des. Test Comput., 2011)

Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. - Xuan-Lun Huang; Ping-Ying Kang; Yuan-Chi Yu; Jiun-Lang Huang (J. Electron. Test., 2011)

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Zhigang Jiang; Lang Tan; Yu Zhang; Yu Hu 001; Wen-Ben Jone; Michael S. Hsiao; James Chien-Mo Li; Jiun-Lang Huang; Lizhen Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling. - Xuan-Lun Huang; Jiun-Lang Huang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Built-In Characterization Technique for 1-Bit/Stage Pipelined ADC. - Y.-H. Chou; Jiun-Lang Huang; Xuan-Lun Huang (Asian Test Symposium, 2012)

A Transition Isolation Scan Cell Design for Low Shift and Capture Power. - Yi-Tsung Lin; Jiun-Lang Huang; Xiaoqing Wen (Asian Test Symposium, 2012)

A SAR ADC missing-decision level detection and removal technique. - Jiun-Lang Huang; X.-L. Huang; Yung-Fa Chou; Ding-Ming Kwai (VTS, 2012)

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. - Xuan-Lun Huang; Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Tseng Kuo-Tsai; Ming-Feng Huang; Yung-Fa Chou; Ding-Ming Kwai (J. Electron. Test., 2012)

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. - Shianling Wu; Laung-Terng Wang; Xiaoqing Wen; Wen-Ben Jone; Michael S. Hsiao; Fangfang Li; James Chien-Mo Li; Jiun-Lang Huang (ACM Trans. Design Autom. Electr. Syst., 2012)

Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. - Shyue-Kung Lu; Hao-Cheng Jheng; Masaki Hashizume; Jiun-Lang Huang; Pony Ning (Asian Test Symposium, 2013)

A mutual characterization based SAR ADC self-testing technique. - H.-J. Lin; Xuan-Lun Huang; Jiun-Lang Huang (ETS, 2013)

An IDDQ-based source driver IC design-for-test technique. - S.-S. Lin; C.-L. Kao; Jiun-Lang Huang; C.-C. Lee; Xuan-Lun Huang (ICCAD, 2013)

A circular pipeline processing based deterministic parallel test pattern generator. - Kuen-Wei Yeh; Jiun-Lang Huang; Hao-Jan Chao; Laung-Terng Wang (ITC, 2013)

Improve speed path identification with suspect path expressions. - Jiun-Lang Huang; Kun-Han Tsai; Yu-Ping Liu; Ruifeng Guo; Manish Sharma; Wu-Tung Cheng (VLSI-DAT, 2013)

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression. - Kazunari Enokimoto; Xiaoqing Wen; Kohei Miyase; Jiun-Lang Huang; Seiji Kajihara; Laung-Terng Wang (VLSI Design, 2013)

Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. - Shyue-Kung Lu; Huan-Hua Huang; Jiun-Lang Huang; Pony Ning (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. - Hsiu-Ming Chang 001; Jiun-Lang Huang; Ding-Ming Kwai; Kwang-Ting Cheng; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

FPGA-Based Subset Sum Delay Lines. - Chung-Yun Wang; Yu-Yi Chen; Jiun-Lang Huang; Xuan-Lun Huang (ATS, 2014)

SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator. - Chun-Hao Chang; Kuen-Wei Yeh; Jiun-Lang Huang; Laung-Terng Wang (ATS, 2015)

A test-application-count based learning technique for test time reduction. - Guo-Yu Lin; Kun-Han Tsai; Jiun-Lang Huang; Wu-Tung Cheng (VLSI-DAT, 2015)

Design and Implementation of an FPGA-Based Data/Timing Formatter. - Yu-Yi Chen; Jiun-Lang Huang; Terry Kuo; Xuan-Lun Huang (J. Electron. Test., 2015)

Design, Automation, and Test for Low-Power and Reliable Flexible Electronics. - Tsung-Ching Jim Huang; Jiun-Lang Huang; Kwang-Ting (Tim) Cheng (Found. Trends Electron. Des. Autom., 2015)

An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing. - Po-Fan Hou; Yi-Tsung Lin; Jiun-Lang Huang; Ann Shih; Zoe F. Conroy (ATS, 2016)

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator. - Kuen-Wei Yeh; Jiun-Lang Huang; Laung-Terng Wang (J. Electron. Test., 2016)

Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature Compensation. - Yang-Kai Huang; Kuan-Te Li; Chih-Lung Hsiao; Chia-An Lee; Jiun-Lang Huang; Terry Kuo (ATS, 2017)

Source code transformation for software-based on-line error detection. - Tsung-Yen Tsai; Jiun-Lang Huang (DSC, 2017)

Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter. - Guan-Hao Hou; Wei-Chen Huang; Jiun-Lang Huang; Terry Kuo (ATS, 2018)

A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction. - Bo-Yi Li; Jiun-Lang Huang (ISOCC, 2018)

Conference Reports: Report on 2017 IEEE Asian Test Symposium. - Jin-Fu Li 001; Jiun-Lang Huang (IEEE Des. Test, 2018)

Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test. - Ching-Yuan Chen; Jiun-Lang Huang (ATS, 2019)

Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. - Kai-Hsun Chen; Ching-Yuan Chen; Jiun-Lang Huang (DDECS, 2019)

An FPGA-Based Data Receiver for Digital IC Testing. - Wei-Chen Huang; Guan-Hao Hou; Jiun-Lang Huang; Terry Kuo (ITC-Asia, 2019)

Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model. - Ching-Yuan Chen; Ching-Hong Cheng; Jiun-Lang Huang; Krishnendu Chakrabarty (ETS, 2020)

Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (ICCAD, 2020)

DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator. - Kuen-Wei Yeh; Jiun-Lang Huang (ITC-Asia, 2020)

Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors. - Kai-Hsun Chen; Bo-Yi Yang; Jia-Ruei Liang; Hung-Lin Chen; Jiun-Lang Huang (ITC-Asia, 2021)

Opportunities for 2.5/3D Heterogeneous SoC Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Chung-Ping Chen (VLSI-DAT, 2021)

Intelligent Design Automation for Heterogeneous Integration. - Iris Hui-Ru Jiang; Yao-Wen Chang; Jiun-Lang Huang; Charlie Chung-Ping Chen (ISPD, 2022)

Test Response Compaction for Software-Based Self-Test. - Jia-Ruei Liang; Ya-Ni Hsieh; Jiun-Lang Huang (ITC-Asia, 2022)

BDD-Based Self-Test Program Generation for Processor Cores. - Hao Cheng; Chi-Jhe Li; Hung-Lin Chen; Jiun-Lang Huang (ITC-Asia, 2023)

SARA: Semantic-assisted Reinforced Active Learning for Entity Alignment. - Ching-Hsuan Liu; Chih-Ming Chen 003; Jing-Kai Lou; Ming-Feng Tsai; Jiun-Lang Huang; Chuan-Ju Wang (IJCNN, 2024)