Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit. - Jiun-Ping Wang; Shiann-Rong Kuang (SiPS, 2007)

Design of power-efficient pipelined truncated multipliers with various output precision. - Shiann-Rong Kuang; Jiun-Ping Wang (IET Comput. Digit. Tech., 2007)

Modified Booth Multipliers With a Regular Partial Product Array. - Shiann-Rong Kuang; Jiun-Ping Wang; Cang-Yuan Guo (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Design of Power-Efficient Configurable Booth Multiplier. - Shiann-Rong Kuang; Jiun-Ping Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Variable-Latency Floating-Point Multipliers for Low-Power Applications. - Shiann-Rong Kuang; Jiun-Ping Wang; Hong-Yi Huang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications. - Jiun-Ping Wang; Shiann-Rong Kuang; Shish-Chang Liang (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems. - Shiann-Rong Kuang; Jiun-Ping Wang; Kai-Cheng Chang; Huan-Wei Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2013)