Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey. - Nadeen Gebara; Jiuxi Meng; Wayne Luk; Paolo Costa (FPT, 2018)

Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. - Shuanglong Liu; Chenglong Zeng; Hongxiang Fan; Ho-Cheung Ng; Jiuxi Meng; Zhiqiang Que; Xinyu Niu; Wayne Luk (FPT, 2018)

Investigating the Feasibility of FPGA-based Network Switches. - Jiuxi Meng; Nadeen Gebara; Ho-Cheung Ng; Paolo Costa; Wayne Luk (ASAP, 2019)

Fast and Accurate Training of Ensemble Models with FPGA-based Switch. - Jiuxi Meng; Ce Guo; Nadeen Gebara; Wayne Luk (ASAP, 2020)

Optimizing Reconfigurable Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Xinyu Niu; Wayne Luk (FCCM, 2020)

High-Performance FPGA Network Switch Architecture. - Philippos Papaphilippou; Jiuxi Meng; Wayne Luk (FPGA, 2020)

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (FPT, 2020)

Mapping Large LSTMs to FPGAs with Weight Reuse. - Zhiqiang Que; Yongxin Zhu 001; Hongxiang Fan; Jiuxi Meng; Xinyu Niu; Wayne Luk (J. Signal Process. Syst., 2020)

Hipernetch: High-Performance FPGA Network Switch. - Philippos Papaphilippou; Jiuxi Meng; Nadeen Gebara; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2022)

Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. - Zhiqiang Que; Hiroki Nakahara; Eriko Nurvitadhi; Andrew Boutros; Hongxiang Fan; Chenglong Zeng; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. - Zhiqiang Que; Hiroki Nakahara; Hongxiang Fan; He Li 008; Jiuxi Meng; Kuen Hung Tsoi; Xinyu Niu; Eriko Nurvitadhi; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2023)