Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. - Jae-Seok Yang; Jiwoo Pak; Xin Zhao 001; Sung Kyu Lim; David Z. Pan (ASP-DAC, 2011)

Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. - Mohit Pathak; Jiwoo Pak; David Z. Pan; Sung Kyu Lim (ICCAD, 2011)

Design for manufacturability and reliability for TSV-based 3D ICs. - David Z. Pan; Sung Kyu Lim; Krit Athikulwongse; Moongon Jung; Joydeep Mitra; Jiwoo Pak; Mohit Pathak; Jae-Seok Yang (ASP-DAC, 2012)

Electromigration-aware routing for 3D ICs with stress-aware EM modeling. - Jiwoo Pak; Sung Kyu Lim; David Z. Pan (ICCAD, 2012)

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs. - Jiwoo Pak; Sung Kyu Lim; David Z. Pan (ICCAD, 2013)

Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs. - Jiwoo Pak; Sung Kyu Lim; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Electromigration-aware redundant via insertion. - Jiwoo Pak; Bei Yu 001; David Z. Pan (ASP-DAC, 2015)

Chip Placement with Deep Reinforcement Learning. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe W. J. Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Sungmin Bae; Azade Nazi; Jiwoo Pak; et al. (CoRR, 2020)

A graph placement methodology for fast chip design. - Azalia Mirhoseini; Anna Goldie; Mustafa Yazgan; Joe Wenjie Jiang; Ebrahim M. Songhori; Shen Wang; Young-Joon Lee; Eric Johnson; Omkar Pathak; Azade Nazi; Jiwoo Pak; Andy Tong; et al. (Nat., 2021)