Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing. - Aibin Yan; Zijie Zhai; Lele Wang 011; Jixiang Zhang 007; Ningning Cui; Tianming Ni; Xiaoqing Wen (ITC-Asia, 2021)

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. - Aibin Yan; Shukai Song; Jixiang Zhang 007; Jie Cui 004; Zhengfeng Huang; Tianming Ni; Xiaoqing Wen; Patrick Girard 001 (ITC-Asia, 2022)