Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization. - Jiying Xue; Zuochang Ye; Yangdong Deng; Hongrui Wang; Liu Yang; Zhiping Yu (ICCAD, 2009)

Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis. - Jiying Xue; Xiaomeng Jiao; Yangdong Deng; Hao Qian 001; Dajie Zeng; Guoyu Li; Zhiping Yu (CIT, 2010)

Full-chip leakage analysis for 65 nm CMOS technology and beyond. - Jiying Xue; Tao Li; Yangdong Deng; Zhiping Yu (Integr., 2010)

A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization. - Jiying Xue; Yangdong Deng; Zuochang Ye; Hongrui Wang; Liu Yang; Zhiping Yu (IEEE Trans. Very Large Scale Integr. Syst., 2012)