Control and Observation of Analog Nodes in Mixed-Signal Boards. - José Silva Matos; Ana C. Leão; João Canas Ferreira (ITC, 1993)

An Approach to Testability Improvement of Mixed-Signal Boards. - José Silva Matos; João Canas Ferreira; Ana C. Leão; José Machado da Silva (ISCAS, 1994)

Architecture of test support ICs for mixed-signal testing. - José Silva Matos; João Canas Ferreira; Ana C. Leão; José Machado da Silva (VTS, 1994)

A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. - João Canas Ferreira; José Silva Matos (FCCM, 1998)

Flexible hardware acceleration for nesting problems. - João Canas Ferreira; José Carlos Alves; Célio Albuquerque 001; José Fernando Oliveira; José Soeiro Ferreira; José Silva Matos (ICECS, 1998)

Mixed hardware/software applications on dynamically reconfigurable hardware. - João Canas Ferreira; José Silva Matos (ICECS, 1998)

FAFNER-Accelerating Nesting Problems with FPGAs. - José Carlos Alves; João Canas Ferreira; C. Albuquerque; José Fernando Oliveira; José Soeiro Ferreira; José Silva Matos (FCCM, 1999)

A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. - João Canas Ferreira; José Silva Matos (FPL, 2004)

Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. - Miguel Lino Silva; João Canas Ferreira (DSD, 2005)

Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. - João Canas Ferreira; Miguel M. Silva (IPDPS, 2005)

Exploiting dynamic reconfiguration of platform FPGAs: implementation issues. - Miguel L. Silva; João Canas Ferreira (IPDPS, 2006)

Support for partial run-time reconfiguration of platform FPGAs. - Miguel Lino Silva; João Canas Ferreira (J. Syst. Archit., 2006)

Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. - Miguel Lino Silva; João Canas Ferreira (IET Comput. Digit. Tech., 2007)

Generation of partial FPGA configurations at run-time. - Miguel Lino Silva; João Canas Ferreira (FPL, 2008)

FPGA-based rectification of stereo images. - João G. P. Rodrigues; João Canas Ferreira (DASIP, 2010)

Creation of Partial FPGA Configurations at Run-Time. - Miguel Lino Silva; João Canas Ferreira (DSD, 2010)

Erlang Inspired Hardware. - Paulo Ferreira 002; João Canas Ferreira; José Carlos Alves (FPL, 2010)

From Instruction Traces to Specialized Reconfigurable Arrays. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (ReConFig, 2011)

Analysis of error detection schemes: Toolchain support and hardware/software implications. - Ali Azarian; João Canas Ferreira; Stephan Werner 002; Zlatko Petrov; João M. P. Cardoso; Michael Hübner 001 (AHS, 2012)

Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. - Fardin Derogarian; João Canas Ferreira; Vítor M. Grade Tavares (DSD, 2012)

A Wearable Sensor Network for Human Locomotion Data Capture. - Andreina Zambrano; Fardin Derogarian; Ruben Dias; Maria José Abreu; André P. Catarino; Ana Maria Rocha; José Machado da Silva; João Canas Ferreira; Vítor Grade Tavares; Miguel Velhote Correia (pHealth, 2012)

A scalable array for Cellular Genetic Algorithms: TSP as case study. - Pedro Vieira dos Santos; José Carlos Alves; João Canas Ferreira (ReConFig, 2012)

Run-time generation of partial FPGA configurations. - Miguel Lino Silva; João Canas Ferreira (J. Syst. Archit., 2012)

Run-time generation of partial FPGA configurations for subword operations. - Miguel Lino Silva; João Canas Ferreira (Microprocess. Microsystems, 2012)

Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (ARC, 2013)

Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. - Filipe Sousa; Francis Anghinolfi; João Canas Ferreira (DSD, 2013)

A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. - Pedro Vieira dos Santos; José Carlos Alves; João Canas Ferreira (FPL, 2013)

Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (Int. J. Reconfigurable Comput., 2013)

Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011). - José Machado da Silva; Sylvie Renaud; João Canas Ferreira (Microelectron. J., 2013)

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. - João Bispo; Nuno Miguel Cardanha Paulino; João M. P. Cardoso; João Canas Ferreira (IEEE Trans. Ind. Informatics, 2013)

A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. - Fardin Derogarian; João Canas Ferreira; Vítor M. Grade Tavares (DSD, 2014)

Design and implementation of hybrid circuit/packet switching for wearable systems. - Fardin Derogarian; João Canas Ferreira; Vítor Grade Tavares (ISIE, 2014)

Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Manuel Paiva Cardoso (ISPA, 2014)

Transparent acceleration of program execution using reconfigurable hardware. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Bispo; João M. P. Cardoso (DATE, 2015)

An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. - Pedro Vieira dos Santos; José Carlos Alves; João Canas Ferreira (DSD, 2015)

Reconfigurable NC-OFDM Processor for 5G Communications. - Mário Lopes Ferreira; João Canas Ferreira (EUC, 2015)

A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks. - Fardin Derogarian; João Canas Ferreira; Vítor M. Grade Tavares (Microprocess. Microsystems, 2015)

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (ACM Trans. Reconfigurable Technol. Syst., 2015)

Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. - Mário Lopes Ferreira; Amin Barahimi; João Canas Ferreira (ARC, 2016)

Dynamically reconfigurable FFT processor for flexible OFDM baseband processing. - Mário Lopes Ferreira; Amin Barahimi; João Canas Ferreira (DTIS, 2016)

An FPGA implementation of a long short-term memory neural network. - João Canas Ferreira; Jose Fonseca (ReConFig, 2016)

A small fully digital open-loop clock and data recovery circuit for wired BANs. - Fardin Derogarian; João Canas Ferreira; Vítor Grade Tavares (Int. J. Circuit Theory Appl., 2016)

Scalable hardware architecture for disparity map computation and object location in real-time. - Pedro Miguel Salgueiro dos Santos; João Canas Ferreira; José Silva Matos (J. Real Time Image Process., 2016)

FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator. - Miguel Carvalho; Mário Lopes Ferreira; João Canas Ferreira (ICECS, 2017)

Towards a type 0 hypervisor for dynamic reconfigurable systems. - Benedikt Janßen; Fatih Korkmaz; Halil Derya; Michael Hübner 001; Mário Lopes Ferreira; João Canas Ferreira (ReConFig, 2017)

Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. - Joao Lopes; Diogo Sousa 002; João Canas Ferreira (ReConFig, 2017)

MICPRO DSD 2015 special issue. - João Canas Ferreira; Paris Kitsos (Microprocess. Microsystems, 2017)

Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. - Mário Lopes Ferreira; João Canas Ferreira; Michael Hübner 001 (ARC, 2018)

Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing. - Helder H. Avelar; João Canas Ferreira (DSD, 2018)

Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. - Mário Lopes Ferreira; João Canas Ferreira (ISCAS, 2018)

Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding. - Fardin Derogarian; João Canas Ferreira; Vítor M. Grade Tavares (J. Mobile Multimedia, 2018)

An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem. - Pedro Vieira dos Santos; José Carlos Alves; João Canas Ferreira (Microprocess. Microsystems, 2018)

Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. - Nuno Miguel Cardanha Paulino; João Canas Ferreira; João M. P. Cardoso (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing. - João Canas Ferreira; Francesca Palumbo (J. Signal Process. Syst., 2019)

Hardware architecture for integrate-and-fire signal reconstruction on FPGA. - Guilherme Carvalho; João Canas Ferreira; Vítor Grade Tavares (DCIS, 2020)

Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. - Nuno Paulino 001; João Canas Ferreira; João Bispo; João M. P. Cardoso (FPL, 2020)

Parallel Implementation of K-Means Algorithm on FPGA. - Leonardo Alves Dias; João Canas Ferreira; Marcelo A. C. Fernandes (IEEE Access, 2020)

Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. - Nuno Paulino 001; João Canas Ferreira; João M. P. Cardoso (IEEE Access, 2020)

A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems. - Fardin Derogarian; João Canas Ferreira; Vítor M. Grade Tavares; José Machado da Silva; Fernando J. Velez (IEEE/ACM Trans. Netw., 2020)

A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications. - Mário Lopes Ferreira; João Canas Ferreira (J. Signal Process. Syst., 2020)

On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. - Tiago Santos; Nuno Paulino 001; João Bispo; João M. P. Cardoso; João Canas Ferreira (FPT, 2021)

A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. - Luís Miguel Sousa; Nuno Miguel Cardanha Paulino; João Canas Ferreira; João Bispo (CoRR, 2021)

Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. - Nuno Paulino 001; João Canas Ferreira; João M. P. Cardoso (ACM Comput. Surv., 2021)

A Binary Translation Framework for Automated Hardware Generation. - Nuno Paulino 001; João Bispo; João Canas Ferreira; João M. P. Cardoso (IEEE Micro, 2021)