Practical experience designing and debugging an FPGA for a real-time ethernet industrial bus. - Matheus Berger Oliveira; Joao de Moraes; Sérgio Luis Cechin; Taisy Silva Weber; Joao Netto (LATS, 2017)

Architecture of an industrial analog input designed to meet safety requirements. - Joao de Moraes; Taisy Silva Weber; Guilherme Muller; Tiago Dall'Agnol; Rafael Macedo; Elaine P. L. Scartezzini; Roque Eduardo Dapper; Sérgio Luis Cechin; Joao Netto (LATS, 2018)