Topological characteristics of logic networks generated by a graph-based methodology. - Maicon Schneider Cardoso; Regis Zanandrea; Renato Souza de Souza; Joao Junior da Silva Machado; Leomar Soares da Rosa Jr.; Felipe de Souza Marques (LASCAS, 2016)

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. - Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Adriel Mota Ziesemer; Felipe S. Marques 001; Leomar S. da Rosa Jr. (LASCAS, 2016)

Transistor placement strategies for non-series-parallel cells. - Maicon Schneider Cardoso; Gustavo H. Smaniotto; Joao Junior da Silva Machado; Matheus T. Moreira; Leomar S. da Rosa; Felipe de Souza Marques (MWSCAS, 2017)