Precise final state determination of mismatched CMOS latches. - Wilhelmus A. M. Van Noije; W. T. Liu; João Navarro Jr. (IEEE J. Solid State Circuits, 1995)

A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems. - João Navarro Jr.; Reinaldo Silveira; Fábio L. Romao; Wilhelmus A. M. Van Noije (Great Lakes Symposium on VLSI, 1997)

CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. - João Navarro Jr.; Wilhelmus A. M. Van Noije (Great Lakes Symposium on VLSI, 1998)

Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology. - João Navarro Jr.; Wilhelmus A. M. Van Noije (Great Lakes Symposium on VLSI, 1998)

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). - João Navarro Soares; Wilhelmus A. M. Van Noije (IEEE J. Solid State Circuits, 1999)

The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data Throughput. - João Navarro Soares; Wilhelmus A. M. Van Noije (SBCCI, 2000)

Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. - João Navarro Jr.; Wilhelmus A. M. Van Noije (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Methodology for CMOS Low Noise Ampli.er Design. - Elkim Roa; João Navarro Soares; Wilhelmus A. M. Van Noije (SBCCI, 2003)

A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. - Fernando P. H. de Miranda; João Navarro Jr.; Wilhelmus A. M. Van Noije (SBCCI, 2004)

A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. - Angel M. Gómez Argüello; João Navarro Jr.; Wilhelmus A. M. Van Noije (SBCCI, 2005)

Mismatch effect analyses in CMOS tapered buffers. - Alexandre J. Aragão; João Navarro Jr.; Wilhelmus A. M. Van Noije (ISCAS, 2006)

A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. - Fernando P. H. de Miranda; João Navarro Jr.; Wilhelmus A. M. Van Noije (ISCAS, 2007)

A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. - Hugo Daniel Hernández; Wilhelmus A. M. Van Noije; Elkim Roa; João Navarro Jr. (SBCCI, 2007)

A 4.1 GHz prescaler using double data throughput E-TSPC structures. - Fernando P. H. de Miranda; João Navarro Jr.; Wilhelmus A. M. Van Noije (SBCCI, 2007)

A simple CMOS bandgap reference circuit with sub-1-V operation. - João Navarro Soares; Eder Ishibe (ISCAS, 2011)

Design of high speed digital circuits with E-TSPC cell library. - João Navarro Jr.; Gustavo Campos Martins (SBCCI, 2011)

Top-down design for Low power Multi-bit Sigma-Delta Modulator. - Heiner Alarcon Cubas; João Navarro Soares Jr. (SBCCI, 2012)

A power optimized decimator for sigma-delta data converters. - Dionisio de Carvalho; João Navarro 001 (LASCAS, 2013)

Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology. - Heiner Alarcon Cubas; João Navarro Soares Jr. (LASCAS, 2013)

A bandgap circuit with a temperature coefficient adjustment block. - Eder Issao Ishibe; João Navarro Soares Junior (MWSCAS, 2013)

A CMOS bandgap reference circuit with a temperature coefficient adjustment block. - Eder Issao Ishibe; João Navarro Soares (SBCCI, 2013)

Design for Stability of Active Inductor with Feedback Resistance. - Gabriel R. Guerreiro; João Navarro 001 (SBCCI, 2014)

Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS. - Arthur Lombardi Campos; João Navarro 001; Maximiliam Luppe (SBCCI, 2019)

Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization. - João Navarro 001; Maximiliam Luppe (SBCCI, 2020)

Charge-Pump Circuit in 65nm CMOS for Neural Stimulation on Deep-Brain Stimulation. - Tiago Mateus Nordi; V. M. Barbosa; R. H. Gounella; Godfred Asan; Maximiliam Luppe; João Navarro Soares Junior; João Paulo Carmo; Erich Talamoni Fonoff; Eduardo Colombari (DCIS, 2021)

A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique. - Lucas Daudt Franck; João Navarro 001; João Paulo Carmo (SBCCI, 2024)

Development of Optrodes and Instrumentation for Wireless Optogenetic Application. - Helder Eiki Oshiro; Rodrigo de A. P. Andrade; João Navarro Soares Junior; Maximiliam Luppe; Eduardo Colombari; M. Celeste Dias; João Paulo Carmo (BIOSTEC (1), 2025)

A Low-Noise Amplifier in Submicron CMOS for Neural Recording on Optogenetics Applications. - Helder Eiki Oshiro; Rodrigo de A. P. Andrade; João Navarro Soares Junior; Maximiliam Luppe; Eduardo Colombari; M. Celeste Dias; João Paulo Carmo (BIOSTEC (1), 2025)