A strategy for testability enhancement at layout level. - João Paulo Teixeira 001; Isabel C. Teixeira; Carlos F. Beltrán Almeida; Fernando M. Gonçalves; Júlio Gonçalves; R. Crespo (EURO-DAC, 1990)

IC Defects-Based Testability Analysis. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (ITC, 1991)

A methodology for testability enhancement at layout level. - João Paulo Teixeira 001; Isabel C. Teixeira; Carlos F. Beltrán Almeida; Fernando M. Gonçalves; Júlio Gonçalves (J. Electron. Test., 1991)

Physical design of testable CMOS digital integrated circuits. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001 (IEEE J. Solid State Circuits, 1991)

Physical DFT for High Coverage of Realistic Faults. - M. Saraiva; P. Casimiro; Marcelino B. Santos; José T. de Sousa; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1992)

On the design of a highly testable cell library. - M. Saraiva; Marcelino B. Santos; A. P. Casimiro; Isabel Maria Cacho Teixeira; João Paulo Teixeira 001 (Microprocess. Microprogramming, 1992)

Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. - A. P. Casimiro; M. Simões; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1993)

Realistic Fault Analysis of CMOS Analog Building Blocks. - P. Nicolau; J. Barbosa; M. Saraiva; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1993)

On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. - A. P. Casimiro; Fernando M. Gonçalves; João Paulo Teixeira 001; Marcelino B. Santos (DFT, 1994)

Fault Modeling and Defect Level Projections in Digital ICs. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Thomas W. Williams (EDAC-ETC-EUROASIC, 1994)

Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. - Mario Calha; Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1994)

Test preparation methodology for high coverage of physical defects in CMOS digital ICs. - Marcelino B. Santos; M. Simões; Isabel C. Teixeira; João Paulo Teixeira 001 (ED&TC, 1995)

Test preparation for high coverage of physical defects in CMOS digital ICs. - Marcelino B. Santos; M. Simões; Isabel C. Teixeira; João Paulo Teixeira 001 (VTS, 1995)

Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. - Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1996)

VHDL fault simulation for defect-oriented test and diagnosis of digital ICs. - João Paulo Teixeira 001; F. Celeiro; L. Dias; J. Ferreira; Marcelino B. Santos (EURO-DAC, 1996)

Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. - F. Celeiro; L. Dias; J. Ferreira; Marcelino B. Santos; João Paulo Teixeira 001 (ITC, 1996)

HW/SW specification using OOM techniques. - Mario Calha; João Paulo Teixeira 001; Isabel C. Teixeira (RSP, 1996)

Defect level evaluation in an IC design environment. - José T. de Sousa; Fernando M. Gonçalves; João Paulo Teixeira 001; Cristoforo Marzocca; Francesco Corsi; Thomas W. Williams (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. - Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 1997)

Defect-oriented testing of analogue and mixed signal ICs. - Marcelino B. Santos; Fernando M. Gonçalves; Michael J. Ohletz; João Paulo Teixeira 001 (ICECS, 1998)

An OO Based Methodology for Real-Time HW/SW Systems Modeling. - Octávio Páscoa Dias; Isabel C. Teixeira; João Paulo Teixeira 001; Carlos Eduardo Pereira (DIPES, 1998)

Defect-oriented test quality assessment using fault sampling and simulation. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 1998)

Sampling Techniques of Non-Equally Probable Faults in VLSI System. - Fernando M. Gonçalves; João Paulo Teixeira 001 (VTS, 1998)

Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. - Marcelino B. Santos; João Paulo Teixeira 001 (DATE, 1999)

From system level to defect-oriented test: a case study. - Octávio Páscoa Dias; Jorge Semião; Marcelino B. Santos; Isabel Maria Cacho Teixeira; João Paulo Teixeira 001 (ETW, 1999)

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Joan Figueras; Salvador Manich; João Paulo Teixeira 001; Marcelino B. Santos (ISCAS (1), 1999)

Teaching Microelectronic-Based Integrated Systems Design and Test. - Fernando M. Gonçalves; João Paulo Teixeira 001 (MSE, 1999)

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (VTS, 1999)

Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures. - Octávio Páscoa Dias; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 1999)

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. - Fernando M. Gonçalves; João Paulo Teixeira 001 (J. Electron. Test., 1999)

RTL-based functional test generation for high defects coverage in digital SOCs. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (ETW, 2000)

Optimizing Functional distribution in Complex System Design. - Octávio Páscoa Dias; Isabel C. Teixeira; João Paulo Teixeira 001; Leandro Buss Becker; Carlos Eduardo Pereira (DIPES, 2000)

MOSYS A Methodology for Automatic Object Identification from System Specification. - Leandro Buss Becker; Carlos Eduardo Pereira; Octávio Páscoa Dias; Isabel C. Teixeira; João Paulo Teixeira 001 (ISORC, 2000)

Quality of Electronic Design: From Architectural Level to Test Coverage. - Octávio Páscoa Dias; Jorge Semião; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ISQED, 2000)

Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip. - Marcelino B. Santos; João Paulo Teixeira 001 (LATW, 2000)

Low Power BIST by Filtering Non-Detecting Vectors. - Salvador Manich; A. Gabarró; M. Lopez; Joan Figueras; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; João Paulo Teixeira 001; Marcelino B. Santos (J. Electron. Test., 2000)

Embedded tutorial: TRP: integrating embedded test and ATE. - Yervant Zorian; Paolo Prinetto; João Paulo Teixeira 001; Isabel C. Teixeira; Carlos Eduardo Pereira; Octávio Páscoa Dias; Jorge Semião; Peter Muhmenthaler; W. Radermacher (DATE, 2001)

Towards E-Management as Enabler for Accelerated Change. - Hugo Lérias; João Luz; Pedro Moura; Ana Mendes; Isabel C. Teixeira; João Paulo Teixeira 001 (ICEIS (2), 2001)

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTW, 2001)

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ITC, 2001)

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2001)

Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 2002)

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. - Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001; Salvador Manich; Rosa Rodríguez-Montañés; Joan Figueras (ITC, 2002)

On High-Quality, Low Energy BIST Preparation at RT-Level. - Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001; Salvador Manich; Luz Balado; Joan Figueras (LATW, 2002)

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2002)

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. - Marcelino B. Santos; Fernando M. Gonçalves; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2002)

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. - Marcelino B. Santos; José M. Fernandes; Isabel C. Teixeira; João Paulo Teixeira 001 (DATE, 2003)

Hardware/software solution for the automation and real-time control of a wine bottling production line. - Rui Ribeiro; Octávio Páscoa Dias; João Paulo Teixeira 001; Isabel C. Teixeira (ETFA (1), 2003)

Fault Simulation Using Partially Reconfigurable Hardware. - Abilio Parreira; João Paulo Teixeira 001; A. Pantelimon; Marcelino B. Santos; José T. de Sousa (FPL, 2003)

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. - Fernando M. Gonçalves; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2003)

A Probabilistic Method for the Computation of Testability of RTL Constructs. - José M. Fernandes; Marcelino B. Santos; Arlindo L. Oliveira; João Paulo Teixeira 001 (DATE, 2004)

FPGAs BIST Evaluation. - Abilio Parreira; João Paulo Teixeira 001; Marcelino B. Santos (FPL, 2004)

Modeling and Simulation of Time Domain Faults in Digital Systems. - Daniel Barros Jr.; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2004)

Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. - Abilio Parreira; João Paulo Teixeira 001; Marcelino B. Santos (Comput. Artif. Intell., 2004)

On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. - Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001; Salvador Manich; Luz Balado; Joan Figueras (J. Electron. Test., 2004)

Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. - Carlos Leong; P. Bento; Pedro Miguel Rodrigues; Andreia Trindade; José C. Silva; Pedro Lousã; Joel Rego; J. Nobre; João Varela; João Paulo Teixeira 001; Isabel C. Teixeira (FPL, 2005)

Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. - Marcial Jesús Rodríguez-Irago; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2005)

Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. - D. Barros Júnior; Marcial Jesús Rodríguez-Irago; Marcelino B. Santos; Isabel C. Teixeira; Fabian Vargas 001; João Paulo Teixeira 001 (J. Electron. Test., 2005)

Probabilistic Testability Analysis and DFT Methods at RTL. - José M. Fernandes; Marcelino B. Santos; Arlindo L. Oliveira; João Paulo Teixeira 001 (DDECS, 2006)

Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. - F. Guerreiro; Jorge Semião; A. Pierce; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DDECS, 2006)

DFT and Probabilistic Testability Analysis at RTL. - José M. Fernandes; Marcelino B. Santos; Arlindo L. Oliveira; João Paulo Cacho Teixeira (HLDVT, 2006)

Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. - Marcial Jesús Rodríguez-Irago; Juan J. Rodríguez-Andina; Fabian Vargas 001; Jorge Semião; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2006)

BIST Architectures and Fault Emulation. - Abilio Parreira; Marcelino B. Santos; João Paulo Teixeira 001 (LATW, 2006)

Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems. - Marcial Jesús Rodríguez-Irago; Juan J. Rodríguez-Andina; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (LATW, 2006)

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DDECS, 2007)

Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. - Jorge Semião; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino Bicho Dos Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 2007)

On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2007)

Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (ISVLSI, 2007)

Functional-oriented mask-based built-in self-test. - Marcelino B. Santos; João Paulo Teixeira 001 (IET Comput. Digit. Tech., 2007)

Robust solution for synchronous communication among multi clock domains. - Jorge Semião; João Varela; Judit Freijedo; Juan J. Rodríguez-Andina; Carlos Leong; João Paulo Teixeira 001; Isabel C. Teixeira (APCCAS, 2008)

Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. - Jorge Semião; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DDECS, 2008)

Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2008)

Signal Integrity Enhancement in Digital Circuits. - Jorge Semião; Marcial Jesús Rodríguez-Irago; Juan J. Rodríguez-Andina; Leonardo Bisch Piccoli; Fabian Vargas 001; Marcelino Bicho Dos Santos; Isabel Maria Cacho Teixeira; João Paulo Teixeira 001 (IEEE Des. Test Comput., 2008)

Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop. - Alex Bystrov; João Paulo Teixeira 001 (J. Low Power Electron., 2008)

Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems. - Judit Freijedo; Jorge Semião; Juan J. Rodríguez-Andina; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Low Power Electron., 2008)

Time Management for Low-Power Design of Digital Systems. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Low Power Electron., 2008)

On-Detector Electronics of the Clear PEM Scanner. - Edgar F. M. Albuquerque; Vasco Bexiga; Ricardo Bugalho; Bruno Carriço; Cláudia S. Ferreira; Miguel Ferreira; Joaquim Godinho; Fernando M. Gonçalves; Carlos Leong; Pedro Lousã; Pedro Machado; Rui Moura; et al. (BIODEVICES, 2009)

Data Acquisition Electronics for PET Mammography Imaging. - Carlos Leong; Pedro Machado; Vasco Bexiga; João Paulo Teixeira 001; Isabel C. Teixeira; Joel Rego; Pedro Neves; Fernando Piedade; Pedro Lousã; Pedro Miguel Rodrigues; Andreia Trindade; Ricardo Bugalho; et al. (BIODEVICES, 2009)

Controllability and observability in mixed signal cores. - José F. da Rocha; Nuno Dias; Angelo Monteiro; Alexandre Neves; Gabriel Santos; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2009)

Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. - Jorge Semião; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2009)

Built-in aging monitoring for safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2009)

Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment. - Jorge Semião; Judit Freijedo; Marlon Moraes; M. Mallmann; Carlos Lemos Antunes; Juliano Benfica; Fabian Vargas 001; Marcelino B. Santos; Isabel C. Teixeira; Juan J. Rodríguez-Andina; João Paulo Teixeira 001; Daniel Lupi; et al. (LATW, 2009)

Programmable aging sensor for automotive safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (DATE, 2010)

Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems. - Carlos Leong; Pedro Machado; Vasco Bexiga; João Paulo Teixeira 001; Isabel C. Teixeira; José C. Silva; Pedro Lousã; João Varela (DDECS, 2010)

Investigating the Use of BICS to detect resistive-open defects in SRAMs. - Raul Chipana; Letícia Maria Veiras Bolzani; Fabian Vargas 001; Jorge Semião; Juan J. Rodríguez-Andina; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2010)

Predictive error detection by on-line aging monitoring. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (IOLTS, 2010)

Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels. - Carlos Leong; João Paulo Teixeira 001; Isabel C. Teixeira; Ricardo Bugalho; Manuel Ferreira 001; Pedro Miguel Rodrigues; José C. Silva; Pedro Lousã; João Varela (ISCAS, 2010)

Low-sensitivity to process variations aging sensor for automotive safety-critical applications. - Julio César Vázquez; Víctor H. Champac; Adriel Ziesemer; Ricardo Reis 001; Isabel Maria Cacho Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (VTS, 2010)

Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance. - Judit Freijedo; Lucía Costas; Jorge Semião; Juan J. Rodríguez-Andina; María José Moure; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Low Power Electron., 2010)

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs. - Vasco Bexiga; Carlos Leong; Jorge Semião; Isabel C. Teixeira; João Paulo Teixeira 001; María Dolores Valdés; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001 (FPL, 2011)

Modeling the effect of process variations on the timing response of nanometer digital circuits. - Judit Freijedo; Jorge Semião; Juan J. Rodríguez-Andina; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (LATW, 2011)

On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications. - R. S. Oliveira; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (LATW, 2011)

Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects. - María Dolores Valdés; Judit Freijedo; María José Moure; Juan J. Rodríguez-Andina; Jorge Semião; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (LATW, 2011)

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. - Celestino V. Martins; Jorge Semião; Julio César Vázquez; Víctor H. Champac; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (VTS, 2011)

Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing. - Judit Freijedo; María Dolores Valdés; Lucía Costas; María José Moure; Juan J. Rodríguez-Andina; Jorge Semião; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Low Power Electron., 2011)

On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications. - R. S. Oliveira; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (J. Low Power Electron., 2011)

The influence of clock-gating on NBTI-induced delay degradation. - Jackson Pachito; Celestino V. Martins; Jorge Semião; Marcelino Bicho Dos Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IOLTS, 2012)

Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. - Jackson Pachito; Celestino V. Martins; Bruno Jacinto; Jorge Semião; Julio César Vázquez; Víctor H. Champac; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (IEEE Des. Test Comput., 2012)

Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. - Judit Freijedo; Jorge Semião; Juan J. Rodríguez-Andina; Fabian Vargas 001; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Electron. Test., 2012)

Aging monitoring with local sensors in FPGA-based designs. - Carlos Leong; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001; María Dolores Valdés; Judit Freijedo; Juan J. Rodríguez-Andina; Fabian Vargas 001 (FPL, 2013)

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. - Julio César Vázquez; Víctor H. Champac; Jorge Semião; Isabel C. Teixeira; Marcelino B. Santos; João Paulo Teixeira 001 (J. Electron. Test., 2013)

Performance sensor for tolerance and predictive detection of delay-faults. - Jorge Semião; David Saraiva; Carlos Leong; André Romão; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (DFT, 2014)

Fault-tolerance in FPGA focusing power reduction or performance enhancement. - Carlos Leong; Jorge Semião; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (LATS, 2015)

Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling. - Carlos Leong; Jorge Semião; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (J. Low Power Electron., 2015)

Performance Sensor for Reliable Operation. - Jorge Semião; Ruben Cabral; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (HCI (8), 2018)

Internet of Things and Artificial Intelligence - A Wining Partnership? - Jorge Semião; Marcelino B. Santos; Isabel C. Teixeira; João Paulo Teixeira 001 (Convergence of Artificial Intelligence and the Internet of Things, 2020)