A scalable multithreaded compiler front-end. - André Windisch; Thomas Schneider 006; Ke Yang; Jochen Mades; Wolfgang Ecker (PARCO, 1999)

An Open VHDL-AMS Simulation Framework. - Thomas Schneider 006; Jochen Mades; Manfred Glesner; André Windisch; Wolfgang Ecker (BMAS, 2000)

VXML: VHDL Hardware Design Representation in XML. - Wolfgang Ecker; Mike Heuchling; Jochen Mades; Thomas Schneider 006; André Windisch; Ke Yang (MBMV, 2000)

A JAVA-Based Mixed-Signal Design Environment. - Jochen Mades; Thomas Schneider 006; Manfred Glesner; André Windisch; Wolfgang Ecker (SBCCI, 2000)

Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). - André Windisch; Thomas Schneider 006; Jochen Mades; Dieter Monjau; Manfred Glesner; Carsten Hammer; Wolfgang Ecker (Informationstechnik Tech. Inform., 2000)

Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. - Jochen Mades; Thomas Schneider 006; André Windisch; Thomas Hollstein; Jürgen Becker 001; Manfred Glesner (MSE, 2001)

Regularization of hierarchical VHDL-AMS models using bipartite graphs. - Jochen Mades; Manfred Glesner (DAC, 2002)

A discrete algorithm for the regularization of hierarchical VHDL-AMS models. - Jochen Mades; Diana Estévez Schwarz; Manfred Glesner (ISCAS (5), 2002)

Strukturelle Konsistenz und Regularisierung von VHDL-AMS-Modellen. - Jochen Mades (Shaker, 2003)

TLS-Level Security for Low Power Industrial IoT Network Infrastructures. - Jochen Mades; Gerd Ebelt; Boris Janjic; Frederik Lauer; Carl Christian Rheinländer; Norbert Wehn (DATE, 2020)