Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications. - Xiaofang Gao; Juin J. Liou; Joe Bernier; Gregg D. Croft; Adelmo Ortiz-Conde (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Optimization of on-chip ESD protection structures for minimal parasitic capacitance. - Xiaofang Gao; Juin J. Liou; Joe Bernier; Gregg D. Croft; Waisum Wong; Satya Vishwanathan (Microelectron. Reliab., 2003)