Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models. - Qing Zhu; Wayne Wei-Ming Dai; Joe G. Xi (ICCAD, 1993)

Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. - Joe G. Xi; Wayne Wei-Ming Dai (DAC, 1995)

Jitter-tolerant clock routing in two-phase synchronous systems. - Joe G. Xi; Wayne Wei-Ming Dai (ICCAD, 1996)

Useful-Skew Clock Routing with Gate Sizing for Low Power Design. - Joe G. Xi; Wayne Wei-Ming Dai (J. VLSI Signal Process., 1997)