Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture. - Elana D. Granston; Eric Stotzer; Joe Zbiciak (OM@PLDI, 2001)

Heterogeneous Multi-processor Coherent Interconnect. - Kai Chirca; Matthew Pierson; Joe Zbiciak; David Thompson; Daniel Wu; Shankar Myilswamy; Roger Griesmer; Kedar Basavaraj; Thomas Huynh; Akshit Dayal; Junbok You; Patrick Eyres; et al. (Hot Interconnects, 2013)

Aquila: A unified, low-latency fabric for datacenter networks. - Dan Gibson; Hema Hariharan; Eric Lance; Moray McLaren; Behnam Montazeri; Arjun Singh; Stephen Wang; Hassan M. G. Wassel; Zhehua Wu; Sunghwan Yoo; Raghuraman Balasubramanian; Prashant Chandra; et al. (NSDI, 2022)