Joel S. Emer

According to our database, Joel S. Emer authored at least 135 papers between 1979 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing.

Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer

ACM Trans. Comput. Syst., 2023

Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era.

Weon Taek Na, Joel S. Emer, Mengjia Yan

CoRR, 2023

Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity.

Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity.

Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators.

Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

SecureLoop: Design Space Exploration of Secure DNN Accelerators.

Kyungmi Lee, Mengjia Yan, Joel S. Emer, Anantha P. Chandrakasan

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Accelerating RTL Simulation with Hardware-Software Co-Design.

Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators.

Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes.

Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!

Tanner Andrulis, Joel S. Emer, Vivienne Sze

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining.

Yifan Yang, Joel S. Emer, Daniel Sánchez

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract).

Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher

Proceedings of the 2023 ACM Workshop on Highlights of Parallel Computing, 2023

Optimizing Compression Schemes for Parallel Sparse Tensor Algebra.

Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer

Proceedings of the Data Compression Conference, 2023

WACO: Learning Workload-Aware Co-optimization of the Format and Schedule of a Sparse Tensor Program.

Jaeyeon Won, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling.

Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

The Sparse Abstract Machine.

Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjølstad

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization.

Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

DAGguise: mitigating memory timing side channels.

Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Simba: scaling deep-learning inference with chiplet-based architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Commun. ACM, 2021

Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future.

Elba Garza, Gururaj Saileshwar, Udit Gupta, Tianyi Liu, Abdulrahman Mahmoud, Saugata Ghose, Joel S. Emer

Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021

Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators.

Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Architecture-Level Energy Estimation for Heterogeneous Computing Systems.

Francis Wang, Yannan Nellie Wu, Matthew E. Woicik, Joel S. Emer, Vivienne Sze

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

SpZip: Architectural Support for Effective Data Compression In Irregular Applications.

Yifan Yang, Joel S. Emer, Daniel Sánchez

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication.

Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Sánchez

Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020

Efficient Processing of Deep Neural Networks

Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01766-7, 2020

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

IEEE J. Solid State Circuits, 2020

Freely scalable and reconfigurable optical hardware for deep learning.

Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel S. Emer, Dirk R. Englund

CoRR, 2020

Estimating Silent Data Corruption Rates Using a Two-Level Model.

Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler

CoRR, 2020

CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches.

Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs.

Yannan Nellie Wu, Vivienne Sze, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices.

Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer, Vivienne Sze

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

ExTensor: An Accelerator for Sparse Tensor Algebra.

Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Timeloop: A Systematic Approach to DNN Accelerator Evaluation.

Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs.

Yannan Nellie Wu, Joel S. Emer, Vivienne Sze

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.

Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany

Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.

Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration.

Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018

DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors.

Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer

IACR Cryptol. ePrint Arch., 2018

Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks.

Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

CoRR, 2018

Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism.

Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

A modular digital VLSI flow for high-productivity SoC design.

Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer

Proceedings of the 55th Annual Design Automation Conference, 2018

Hardware for machine learning: Challenges and opportunities.

Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies.

Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Michael Adler, Joel S. Emer

ACM Trans. Reconfigurable Technol. Syst., 2017

Efficient Processing of Deep Neural Networks: A Tutorial and Survey.

Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer

Proc. IEEE, 2017

Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators.

Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

IEEE Micro, 2017

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks.

Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze

IEEE J. Solid State Circuits, 2017

Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision.

Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

CoRR, 2017

Understanding error propagation in deep learning neural network (DNN) accelerators and applications.

Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler

Proceedings of the International Conference for High Performance Computing, 2017

SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation.

Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer

Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper).

Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism.

Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.

Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Automatic Construction of Program-Optimized FPGA Memory Networks.

Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

A method to estimate the energy consumption of deep neural networks.

Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

SAM: Optimizing Multithreaded Cores for Speculative Parallelism.

Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Unlocking Ordered Parallelism with the Swarm Architecture.

Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez

IEEE Micro, 2016

Data-centric execution of speculative parallel programs.

Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

CLARA: Circular Linked-List Auto and Self Refresh Architecture.

Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler

Proceedings of the Second International Symposium on Memory Systems, 2016

14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks.

Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks.

Yu-Hsin Chen, Joel S. Emer, Vivienne Sze

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning.

Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.

Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer

ACM Trans. Comput. Syst., 2015

A fast and accurate analytical technique to compute the AVF of sequential bits in a processor.

Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer

Proceedings of the 48th International Symposium on Microarchitecture, 2015

A scalable architecture for ordered parallelism.

Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez

Proceedings of the 48th International Symposium on Microarchitecture, 2015

High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches.

Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Scavenger: Automating the construction of application-optimized memory hierarchies.

Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Efficient Spatial Processing Element Control via Triggered Instructions.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

IEEE Micro, 2014

Exploiting spatial architectures for edit distance algorithms.

Jesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

The LEAP FPGA operating system.

Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories.

Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

Using in-flight chains to build a scalable cache coherence protocol.

Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer

ACM Trans. Archit. Code Optim., 2013

Triggered instructions: a control paradigm for spatially-programmed architectures.

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A Hierarchical Architectural Framework for Reconfigurable Logic Computing.

Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Optimizing under abstraction: Using prefetching to improve FPGA performance.

Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

The gradient-based cache partitioning algorithm.

William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer

ACM Trans. Archit. Code Optim., 2012

Scheduling heterogeneous multi-cores through performance impact estimation (PIE).

Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

ZIP-IO: Architecture for application-specific compression of Big Data.

Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Leveraging latency-insensitivity to ease multiple FPGA design.

Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

CRUISE: cache replacement and utility-aware scheduling.

Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011

DEC Alpha.

Joel S. Emer, Tryggve Fossum

Proceedings of the Encyclopedia of Parallel Computing, 2011

PACMan: prefetch-aware cache management for high performance caching.

Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

SHiP: signature-based hit predictor for high performance caching.

Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing.

Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Leap scratchpads: automatic memory and cache management for reconfigurable logic.

Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010

The Future of Architectural Simulation.

James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi

IEEE Micro, 2010

Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies.

Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID).

Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

High performance cache replacement using re-reference interval prediction (RRIP).

Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

ACM Trans. Reconfigurable Technol. Syst., 2009

Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences.

Joel S. Emer, Dean M. Tullsen

IEEE Micro, 2009

Accelerating architecture research.

Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.

Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Soft connections: addressing the hardware-design modularity problem.

Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer

Proceedings of the 46th Design Automation Conference, 2009

2008

Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching.

Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer

IEEE Micro, 2008

Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal.

Arijit Biswas, Paul Racunas, Joel S. Emer, Shubhendu S. Mukherjee

IEEE Comput. Archit. Lett., 2008

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.

Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Adaptive insertion policies for managing shared caches.

Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007

Single-Threaded vs. Multithreaded: Where Should We Focus?

Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag

IEEE Micro, 2007

Late-binding: enabling unordered load-store queues.

Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Adaptive insertion policies for high performance caching.

Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2005

Computing Architectural Vulnerability Factors for Address-Based Structures.

Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

The Soft Error Problem: An Architectural Perspective.

Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

Reducing the Soft-Error Rate of a High-Performance Microprocessor.

Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt

IEEE Micro, 2004

Cache Scrubbing in Microprocessors: Myth or Necessity?

Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor.

Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003

Measuring Architectural Vulnerability Factors.

Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin

IEEE Micro, 2003

A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor.

Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2002

Performance Simulation Tools.

Shubhendu S. Mukherjee, Sarita V. Adve, Todd M. Austin, Joel S. Emer, Peter S. Magnusson

Computer, 2002

Asim: A Performance Model Framework.

Joel S. Emer, Pritpal S. Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan

Computer, 2002

Tarantula: A Vector Extension to the Alpha Architecture.

Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec

Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002

Loose Loops Sink Chips.

Eric Borch, Eric Tune, Srilatha Manne, Joel S. Emer

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

A comparative study of arbitration algorithms for the Alpha 21364 pipelined router.

Shubhendu S. Mukherjee, Federico Silla, Peter J. Bannon, Joel S. Emer, Steven Lang, David Webb

Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2000

Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing.

Harish Patil, Joel S. Emer

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

The Use of Multithreading for Exception Handling.

Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi

Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Reducing cache misses using hardware and software page placement.

Timothy Sherwood, Brad Calder, Joel S. Emer

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Retrospective: Characterization of Processor Performance in the VAX-11/780.

Joel S. Emer, Douglas W. Clark

Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Memory Dependence Prediction Using Store Sets.

George Z. Chrysos, Joel S. Emer

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1997

Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.

Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen

ACM Trans. Comput. Syst., 1997

Simultaneous multithreading: a platform for next-generation processors.

Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, Dean M. Tullsen

IEEE Micro, 1997

A Language for Describing Predictors and Its Application to Automatic Synthesis.

Joel S. Emer, Nicholas C. Gloy

Proceedings of the 24th International Symposium on Computer Architecture, 1997

1996

Incremental Versus Revolutionary Research.

Joel S. Emer

ACM Comput. Surv., 1996

Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor.

Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm

Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

Predictive Sequential Associative Cache.

Brad Calder, Dirk Grunwald, Joel S. Emer

Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1995

A system level perspective on branch architecture performance.

Brad Calder, Dirk Grunwald, Joel S. Emer

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Instruction Fetching: Coping with Code Bloat.

Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1989

Performance Analysis of Mass Storage Service Alternatives for Distributed Systems.

K. K. Ramakrishnan, Joel S. Emer

IEEE Trans. Software Eng., 1989

1988

Performance Considerations for Distributed Services: A Case Study: Mass Storage.

Joel S. Emer, K. K. Ramakrishnan

Proceedings of the 8th International Conference on Distributed Computing Systems, 1988

1986

Design analysis of a heterogeneous distributed system.

Joel S. Emer, K. K. Ramakrishnan

Proceedings of the 2nd ACM SIGOPS European Workshop, 1986

1985

Performance of the VAX-11/780 Translation Buffer: Simulation and Measurement

Douglas W. Clark, Joel S. Emer

ACM Trans. Comput. Syst., 1985

1984

A Characterization of Processor Performance in the VAX-11/780.

Joel S. Emer, Douglas W. Clark

Proceedings of the 11th Annual Symposium on Computer Architecture, 1984

1979

Shared Resources for Multiple Instruction Stream Pipelined Processors

Joel S. Emer

PhD thesis, 1979