Race Detection for Two-Phase Systems. - Joel Grodstein; Jim Montanaro; Susanne Marino (ICCAD, 1990)

Constraint Identification for Timing Verification. - Joel Grodstein; Jengwei Pan; William J. Grundmann; Bruce Gieseke; Yao-Tsung Yen (ICCAD, 1990)

Timing Verification on a 1.2M-Device Full-Custom CMOS Design. - Jengwei Pan; Larry L. Biro; Joel Grodstein; William J. Grundmann; Yao-Tsung Yen (DAC, 1991)

Automatic Detection of MOS Synchronizers for Timing Verification. - Joel Grodstein; Nick Rethman; Rahul Razdan; Gabriel P. Bischoff (ICCAD, 1991)

A simple algorithm for fanout optimization using high-performance buffer libraries. - K. Kodandapani; Joel Grodstein; Antun Domic; Hervé J. Touati (ICCAD, 1993)

Optimal latch mapping and retiming within a tree. - Joel Grodstein; Eric Lehman; Heather Harkness; Hervé J. Touati; Bill Grundmann (ICCAD, 1994)

A delay model for logic synthesis of continuously-sized networks. - Joel Grodstein; Eric Lehman; Heather Harkness; Bill Grundmann; Yosinori Watanabe (ICCAD, 1995)

Logic decomposition during technology mapping. - Eric Lehman; Yosinori Watanabe; Joel Grodstein; Heather Harkness (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Static race verification for networks with reconvergent clocks. - Joel Grodstein; Nick Rethman; Nevine Nassif (ICCD, 1998)

A low-cost, 300-MHz, RISC CPU with attached media processor. - Sribalan Santhanam; Allen J. Baum; David Bertucci; Mike Braganza; Kevin Broch; Todd Broch; James Burnette; Edward Chang; Kwong-Tak Chui; Dan Dobberpuhl; Paul M. Donahue; Joel Grodstein; et al. (IEEE J. Solid State Circuits, 1998)

Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. - Joel Grodstein; Rachid Rayess; Tad Truex; Linda Shattuck; Sue Lowell; Dan Bailey; David Bertucci; Gabriel P. Bischoff; Daniel E. Dever; Mike Gowan; Roy Lane; Brian Lilly; et al. (ACM Great Lakes Symposium on VLSI, 2002)

Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. - Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (IWLS, 2002)

Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. - Joel Grodstein; Dilip K. Bhavsar; Vijay Bettada; Richard A. Davies (ICCD, 2003)

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. - Hui-Yuan Song; S. Bohidar; R. Iris Bahar; Joel Grodstein (ICCD, 2003)

RESTA: a robust and extendable symbolic timing analysis tool. - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (ACM Great Lakes Symposium on VLSI, 2004)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Timing analysis for full-custom circuits using symbolic DC formulations. - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Accurate timing analysis using SAT and pattern-dependent delay models. - Desta Tadesse; D. Sheffield; E. Lenge; R. Iris Bahar; Joel Grodstein (DATE, 2007)

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. - Desta Tadesse; R. Iris Bahar; Joel Grodstein (VTS, 2008)

AutoRex: An automated post-silicon clock tuning tool. - Desta Tadesse; Joel Grodstein; R. Iris Bahar (ITC, 2009)

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. - Desta Tadesse; R. Iris Bahar; Joel Grodstein (J. Electron. Test., 2011)