Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. - Joeri De Vos; Vladimir Cherman; Mikael Detalle; Teng Wang; Abdellah Salahouelhadj; Robert Daily; Geert Van der Plas; Eric Beyne (3DIC, 2014)

Thermal experimental and modeling analysis of high power 3D packages. - Herman Oprins; Vladimir Cherman; Geert Van der Plas; F. L. T. Maggioni; Joeri De Vos; Eric Beyne (ICICDT, 2015)

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. - Stefaan Van Huylenbroeck; Yunlong Li; Michele Stucchi; Lieve Bogaerts; Joeri De Vos; Gerald Beyer; Eric Beyne; Mohand Brouri; Praveen Nalla; Sanjay Gopinath; Matthew Thorum; Joe Richardson; et al. (3DIC, 2016)

Extreme wafer thinning optimization for via-last applications. - Anne Jourdain; Joeri De Vos; Fumihiro Inoue; Kenneth J. Rebibis; Andy Miller; Gerald Beyer; Eric Beyne; Edward Walsby; Jash Patel; Oliver Ansell; Janet Hopkins; Huma Ashraf; et al. (3DIC, 2016)

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. - C. Roda Neve; Mikael Detalle; Philip Nolmans; Yunlong Li; Joeri De Vos; Geert Van der Plas; Gerald Beyer; Eric Beyne (3DIC, 2016)

Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects. - Joeri De Vos; Lan Peng; Alain Phommahaxay; Joost Van Ongeval; Andy Miller; Eric Beyne; Florian Kurz; Thomas Wagenleiter; Markus Wimplinger; Thomas Uhrmann (3DIC, 2016)

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. - Luka Kljucar; Mario Gonzalez; Kristof Croes; Ingrid De Wolf; Joke De Messemaeker; Gayle Murdoch; Philip Nolmans; Joeri De Vos; Jürgen Bömmels; Eric Beyne; Zsolt Tökei (Microelectron. Reliab., 2017)

A study on substrate noise coupling among TSVs in 3D chip stack. - Yuuki Araga; Makoto Nagata; Joeri De Vos; Geert Van der Plas; Eric Beyne (IEICE Electron. Express, 2018)

Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. - Masahide Goto; Joeri De Vos; Toshihisa Watabe; Kei Hagiwara; Masakazu Nanba; Yoshinori Iguchi; Eiji Higurashi; Yuki Honda; Takuya Saraya; Masaharu Kobayashi; Hiroshi Toshiyoshi; Toshiro Hiramoto (3DIC, 2019)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)