Automated design of operational transconductance amplifiers using reversed geometric programming. - Johan P. Vanderhaegen; Robert W. Brodersen (DAC, 2004)

Background ADC calibration in digital domain. - Cheongyuen W. Tsang; Yun Chiu; Johan P. Vanderhaegen; Sebastian Hoyos; Charles Chen; Robert W. Brodersen; Borivoje Nikolic (CICC, 2008)

A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. - Sebastian Hoyos; Cheongyuen W. Tsang; Johan P. Vanderhaegen; Yun Chiu; Yasutoshi Aibara; Haideh Khorramabadi; Borivoje Nikolic (ESSCIRC, 2008)

A 6.7nV/√Hz Sub-mHz-1/f-corner 14b analog-to-digital interface for rail-to-rail precision voltage sensing. - Chinwuba D. Ezekwe; Johan P. Vanderhaegen; Xinyu Xing; Ganesh K. Balachandran (ISSCC, 2011)

A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. - Sebastian Hoyos; Cheongyuen W. Tsang; Johan P. Vanderhaegen; Yun Chiu; Yasutoshi Aibara; Haideh Khorramabadi; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Session 34 Overview: Emerging Imaging Solutions Imagers, Medical, Mems and Displays Subcommittee. - Kazuko Nishimura; Johan P. Vanderhaegen; Matteo Perenzoni (ISSCC, 2021)