Investigating modern layout representations for improved 3d design automation. - Robert Fischbach; Jens Lienig; Johann Knechtel (ACM Great Lakes Symposium on VLSI, 2011)

Assembling 2D blocks into 3D chips. - Johann Knechtel; Igor L. Markov; Jens Lienig (ISPD, 2011)

Multiobjective optimization of deadspace, a critical resource for 3D-IC integration. - Johann Knechtel; Igor L. Markov; Jens Lienig; Matthias Thiele (ICCAD, 2012)

Assembling 2-D Blocks Into 3-D Chips. - Johann Knechtel; Igor L. Markov; Jens Lienig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Integration of thermal management and floorplanning based on three-dimensional layout representations. - Puskar Budhathoki; Johann Knechtel; Andreas Henschel; Ibrahim Abe M. Elfadel (ICECS, 2013)

Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. - Robert Fischbach; Johann Knechtel; Jens Lienig (ISPD, 2013)

Structural planning of 3D-IC interconnects by block alignment. - Johann Knechtel; Evangeline F. Y. Young; Jens Lienig (ASP-DAC, 2014)

Planning Massive Interconnects in 3-D Chips. - Johann Knechtel; Evangeline F. Y. Young; Jens Lienig (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Physical Design Automation for 3D Chip Stacks: Challenges and Solutions. - Johann Knechtel; Jens Lienig (ISPD, 2016)

On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. - Johann Knechtel; Ozgur Sinanoglu (DAC, 2017)

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques. - Abhrajit Sengupta; Satwik Patnaik; Johann Knechtel; Mohammed Ashraf; Siddharth Garg; Ozgur Sinanoglu (ICCAD, 2017)

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. - Johann Knechtel; Ozgur Sinanoglu; Ibrahim Abe M. Elfadel; Jens Lienig; Cliff C. N. Sze (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

Optimal die placement for interposer-based 3D ICs. - Sergii Osmolovskyi; Johann Knechtel; Igor L. Markov; Jens Lienig (ASP-DAC, 2018)

Concerted wire lifting: Enabling secure and cost-effective split manufacturing. - Satwik Patnaik; Johann Knechtel; Mohammed Ashraf; Ozgur Sinanoglu (ASP-DAC, 2018)

Raise your game for split manufacturing: restoring the true functionality through BEOL. - Satwik Patnaik; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu (DAC, 2018)

Advancing hardware security using polymorphic and stochastic spin-hall effect devices. - Satwik Patnaik; Nikhil Rangarajan; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (DATE, 2018)

Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (ICCAD, 2018)

Multi-Objective 3D Floorplanning with Integrated Voltage Assignment. - Johann Knechtel; Jens Lienig; Ibrahim Abe M. Elfadel (ACM Trans. Design Autom. Electr. Syst., 2018)

Protect Your Chip Design Intellectual Property: An Overview. - Johann Knechtel; Satwik Patnaik; Ozgur Sinanoglu (COINS, 2019)

Attacking Split Manufacturing from a Deep Learning Perspective. - Haocheng Li; Satwik Patnaik; Abhrajit Sengupta; Haoyu Yang; Johann Knechtel; Bei Yu 001; Evangeline F. Y. Young; Ozgur Sinanoglu (DAC, 2019)

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. - Abhrajit Sengupta; Mohammed Nabeel 001; Johann Knechtel; Ozgur Sinanoglu (DATE, 2019)

3D Integration: Another Dimension Toward Hardware Security. - Johann Knechtel; Satwik Patnaik; Ozgur Sinanoglu (IOLTS, 2019)

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets. - Mohammed Nabeel 001; Mohammed Ashraf; Satwik Patnaik; Vassos Soteriou; Ozgur Sinanoglu; Johann Knechtel (CoRR, 2019)

Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators. - Johann Knechtel; Jacek Gosciniak; Alabi Bojesomo; Satwik Patnaik; Ozgur Sinanoglu; Mahmoud Rasras (CoRR, 2019)

Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Des. Test, 2019)

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA. - Johann Knechtel; Elif Bilge Kavun; Francesco Regazzoni 001; Annelie Heuser; Anupam Chattopadhyay; Debdeep Mukhopadhyay; Soumyajit Dey; Yunsi Fei; Yaacov Belenky; Itamar Levi; Tim Güneysu; Patrick Schaumont; et al. (DATE, 2020)

Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. - Johann Knechtel (ISPD, 2020)

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Access, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (CoRR, 2020)

Power Side-Channel Attacks in Negative Capacitance Transistor. - Johann Knechtel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Yogesh Singh Chauhan; Jörg Henkel; Ozgur Sinanoglu; Hussam Amrouch (IEEE Micro, 2020)

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets. - Mohammed Nabeel 001; Mohammed Ashraf; Satwik Patnaik; Vassos Soteriou; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Computers, 2020)

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime. - Satwik Patnaik; Nikhil Rangarajan; Johann Knechtel; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Security Closure of Physical Layouts ICCAD Special Session Paper. - Johann Knechtel; Jayanth Gopinath; Jitendra Bhandari; Mohammed Ashraf; Hussam Amrouch; Shekhar Borkar; Sung Kyu Lim; Ozgur Sinanoglu; Ramesh Karri (ICCAD, 2021)

Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper. - Jens Lienig; Susann Rothe; Matthias Thiele; Nikhil Rangarajan; Mohammed Ashraf; Mohammed Nabeel 001; Hussam Amrouch; Ozgur Sinanoglu; Johann Knechtel (ICCAD, 2021)

Hardware Security for and beyond CMOS Technology. - Johann Knechtel (ISPD, 2021)

Interposer-Based Root of Trust. - Tapojyoti Mandal; Gino Chacon; Johann Knechtel; Ozgur Sinanoglu; Paul Gratz; Vassos Soteriou (CoRR, 2021)

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. - Haocheng Li; Satwik Patnaik; Mohammed Ashraf; Haoyu Yang; Johann Knechtel; Bei Yu 001; Ozgur Sinanoglu; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects. - Satwik Patnaik; Mohammed Ashraf; Ozgur Sinanoglu; Johann Knechtel (IEEE Trans. Emerg. Top. Comput., 2021)

UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. - Lilas Alrahis; Satwik Patnaik; Johann Knechtel; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2021)

Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest. - Johann Knechtel; Jayanth Gopinath; Mohammed Ashraf; Jitendra Bhandari; Ozgur Sinanoglu; Ramesh Karri (ISPD, 2022)

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. - Nikhil Rangarajan; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Shubham Rai; Gopal Raut; Heba Abunahla; Baker Mohammad; Santosh Kumar Vishvakarma; Akash Kumar 001; Johann Knechtel; Ozgur Sinanoglu (ISVLSI, 2022)

Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. - Gino A. Chacon; Charles Williams; Johann Knechtel; Ozgur Sinanoglu; Paul V. Gratz (IEEE Comput. Archit. Lett., 2022)

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL. - Abhrajit Sengupta; Mohammed Nabeel 001; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu (Cryptogr., 2022)

SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. - Nikhil Rangarajan; Johann Knechtel; Dinesh Rajasekharan; Ozgur Sinanoglu (IEEE Embed. Syst. Lett., 2022)

IsoLock: Thwarting Link-Prediction Attacks on Routing Obfuscation by Graph Isomorphism. - Shaza Elsharief; Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2022)

Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. - Johann Knechtel; Tarek Ashraf; Natascha Fernengel; Satwik Patnaik; Mohammed Nabeel 001; Mohammed Ashraf; Ozgur Sinanoglu; Hussam Amrouch (Integr., 2022)

GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. - Lilas Alrahis; Johann Knechtel; Florian Klemme; Hussam Amrouch; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. - Lilas Alrahis; Abhrajit Sengupta; Johann Knechtel; Satwik Patnaik; Hani H. Saleh; Baker Mohammad; Mahmoud Al-Qutayri; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing. - Satwik Patnaik; Mohammed Ashraf; Haocheng Li; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating. - Nikhil Rangarajan; Johann Knechtel; Nimisha Limaye; Ozgur Sinanoglu; Hussam Amrouch (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits. - Shubham Rai; Satwik Patnaik; Ansh Rupani; Johann Knechtel; Ozgur Sinanoglu; Akash Kumar 001 (IEEE Trans. Emerg. Top. Comput., 2022)

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices. - Nikhil Rangarajan; Satwik Patnaik; Johann Knechtel; Ramesh Karri; Ozgur Sinanoglu; Shaloo Rakheja (IEEE Trans. Emerg. Top. Comput., 2022)

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. - Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (ASP-DAC, 2023)

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning. - Animesh Basak Chowdhury; Lilas Alrahis; Luca Collini; Johann Knechtel; Ramesh Karri; Siddharth Garg; Ozgur Sinanoglu; Benjamin Tan 001 (DAC, 2023)

TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection. - Hazem Lashen; Lilas Alrahis; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2023)

Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. - Mohammad Eslami; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri; Samuel Pagliarini (ISPD, 2023)

X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks. - Saideep Sreekumar; Mohammed Ashraf; Mohammed Thari Nabeel; Ozgur Sinanoglu; Johann Knechtel (ISPD, 2023)

Security Closure of IC Layouts Against Hardware Trojans. - Fangzhou Wang; Qijing Wang; Bangqi Fu; Shui Jiang; Xiaopeng Zhang 009; Lilas Alrahis; Ozgur Sinanoglu; Johann Knechtel; Tsung-Yi Ho; Evangeline F. Y. Young (ISPD, 2023)

UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks. - Lilas Alrahis; Likhitha Mankali; Satwik Patnaik; Abhrajit Sengupta; Johann Knechtel; Ozgur Sinanoglu (SPACE, 2023)

DEFending Integrated Circuit Layouts. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ramesh Karri (IACR Cryptol. ePrint Arch., 2023)

Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. - Likhitha Mankali; Lilas Alrahis; Satwik Patnaik; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Inf. Forensics Secur., 2023)

VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques. - Likhitha Mankali; Satwik Patnaik; Nimisha Limaye; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Safeguarding the Silicon: Strategies for Integrated Circuit Layout Protection. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (APCCAS, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (ICCAD, 2024)

Selective Forgetting in Task-Progressive Learning Through Machine Unlearning. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ICMLC, 2024)

Obfuscation of FSMs for Secure Outsourcing of Neural Network Inference onto FPGAs. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2024)

Code-Based Cryptography for Confidential Inference on FPGAs: An End-to-End Methodology. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ISQED, 2024)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust. - Zeng Wang; Lilas Alrahis; Likhitha Mankali; Johann Knechtel; Ozgur Sinanoglu (ISVLSI, 2024)

The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security. - Lilas Alrahis; Mohammed Thari Nabeel; Johann Knechtel; Ozgur Sinanoglu (VLSI-SoC, 2024)

MCS-NTT: Multi-Chip System Design for NTT Acceleration. - Mohammed Nabeel 001; Homer Gamil; Johann Knechtel; Michail Maniatakos (VLSI-SoC, 2024)

Lightweight Masking Against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Thari Nabeel; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (CoRR, 2024)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. - Fangzhou Wang; Qijing Wang; Lilas Alrahis; Bangqi Fu; Shui Jiang; Xiaopeng Zhang 009; Ozgur Sinanoglu; Tsung-Yi Ho; Evangeline F. Y. Young; Johann Knechtel (CoRR, 2024)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines. - Jitendra Bhandari; Johann Knechtel; Ramesh Narayanaswamy; Siddharth Garg; Ramesh Karri (CoRR, 2024)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search. - Jitendra Bhandari; Animesh Basak Chowdhury; Mohammed Nabeel 001; Ozgur Sinanoglu; Siddharth Garg; Ramesh Karri; Johann Knechtel (CoRR, 2024)

NiLoPher: Breaking a Modern SAT-Hardened Logic-Locking Scheme via Power Analysis Attack. - Prithwish Basu Roy; Johann Knechtel; Akashdeep Saha; Saideep Sreekumar; Likhitha Mankali; Mohammed Thari Nabeel; Debdeep Mukhopadhyay; Ramesh Karri; Ozgur Sinanoglu (IACR Cryptol. ePrint Arch., 2024)

Progressive Learning With Recurrent Neural Network for Sequence Classification. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. - Gino A. Chacon; Charles Williams; Johann Knechtel; Ozgur Sinanoglu; Paul V. Gratz; Vassos Soteriou (ACM Trans. Archit. Code Optim., 2024)

Beware Your Standard Cells! On Their Role in Static Power Side-Channel Attacks. - Jitendra Bhandari; Likhitha Mankali; Mohammed Nabeel 001; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. - Lakshmi Likhitha Mankali; Jitendra Bhandari; Manaar Alam; Ramesh Karri; Michail Maniatakos; Ozgur Sinanoglu; Johann Knechtel (DATE, 2025)

Logic Locking for Random Forests: Securing HDL Design and FPGA Accelerator Implementation. - Rupesh Raj Karn; Johann Knechtel; Ozgur Sinanoglu (ICISSP (2), 2025)

LiCSPA: Lightweight Countermeasure against Static Power Side-Channel Attacks. - Jitendra Bhandari; Mohammed Nabeel 001; Likhitha Mankali; Ozgur Sinanoglu; Ramesh Karri; Johann Knechtel (ISCAS, 2025)

Educational Framework for Power Side-Channel Attacks on Neural Networks in Embedded Systems. - Rupesh Raj Karn; Prithwish Basu Roy; Johann Knechtel; Ozgur Sinanoglu (ISCAS, 2025)

GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced Robustness. - Akashdeep Saha; Prithwish Basu Roy; Johann Knechtel; Ramesh Karri; Ozgur Sinanoglu; Lilas Alrahis (VTS, 2025)

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. - Johann Knechtel; Mohammad Eslami; Peng Zou; Min Wei; Xingyu Tong 001; Binggang Qiu; Zhijie Cai; Guohao Chen 001; Benchao Zhu; Jiawei Li; Jun Yu 010; Jianli Chen; et al. (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

DEFending Integrated Circuit Layouts. - Jitendra Bhandari; Jayanth Gopinath; Mohammed Ashraf; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Inf. Forensics Secur., 2025)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding. - Zeng Wang; Minghao Shao; Mohammed Nabeel 001; Prithwish Basu Roy; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammed Shafique 001; Johann Knechtel (CoRR, 2025)

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination. - Zeng Wang; Minghao Shao; Jitendra Bhandari; Likhitha Mankali; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form. - Prithwish Basu Roy; Akashdeep Saha; Manaar Alam; Johann Knechtel; Michail Maniatakos; Ozgur Sinanoglu; Ramesh Karri (CoRR, 2025)

SALAD: Systematic Assessment of Machine Unlearing on LLM-Aided Hardware Design. - Zeng Wang; Minghao Shao; Rupesh Raj Karn; Likhitha Mankali; Jitendra Bhandari; Ramesh Karri; Ozgur Sinanoglu; Muhammad Shafique 001; Johann Knechtel (CoRR, 2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. - Raghu Vamshi Hemadri; Jitendra Bhandari; Andre Nakkab; Johann Knechtel; Badri P. Gopalan; Ramesh Narayanaswamy; Ramesh Karri; Siddharth Garg (CoRR, 2025)