Reverse Engineering of Cryptographic Cores by Structural Interpretation Through Graph Analysis. - Michael Werner; Bernhard Lippmann; Johanna Baehr 001; Helmut Gräb (IVSW, 2018)

Improving on State Register Identification in Sequential Hardware Reverse Engineering. - Michaela Brunner; Johanna Baehr 001; Georg Sigl (HOST, 2019)

Machine learning and structural characteristics for reverse engineering. - Johanna Baehr 001; Alessandro Bernardini; Georg Sigl; Ulf Schlichtmann (Integr., 2020)

Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. - Alexander Hepp; Johanna Baehr 001; Georg Sigl (DATE, 2022)

Physical and Functional Reverse Engineering Challenges for Advanced Semiconductor Solutions. - Bernhard Lippmann; Ann-Christin Bette; Matthias Ludwig 005; Johannes Mutter; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser; Nicola Kovac; Tobias Zweifel; Martin Rasche; Oliver Kellermann (DATE, 2022)

Hardware Obfuscation of Digital FIR Filters. - Levent Aksoy; Alexander Hepp; Johanna Baehr 001; Samuel Pagliarini (DDECS, 2022)

Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. - Johanna Baehr 001; Alexander Hepp; Michaela Brunner; Maja Malenko; Georg Sigl (DSD, 2022)

Toward a Human-Readable State Machine Extraction. - Michaela Brunner; Alexander Hepp; Johanna Baehr 001; Georg Sigl (ACM Trans. Design Autom. Electr. Syst., 2022)

Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. - Michaela Brunner; Hye-Hyun Lee; Alexander Hepp; Johanna Baehr 001; Georg Sigl (DDECS, 2024)

Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. - Michael Mildner; Michaela Brunner; Michael Gruber; Johanna Baehr 001; Georg Sigl (DDECS, 2024)

Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC). - Bernhard Lippmann; Johanna Baehr 001; Alexander Hepp; Horst A. Gieser (DATE, 2025)