A Fast and Accurate FPGA-Based Fault Injection System. - Thomas Schweizer; Dustin Peterson; Johannes Maximilian Kühn; Tommy Kuhn; Wolfgang Rosenstiel (FCCM, 2013)

Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection. - Johannes Maximilian Kühn; Thomas Schweizer; Dustin Peterson; Tommy Kuhn; Wolfgang Rosenstiel (FPT, 2013)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

Fined-grained body biasing for frequency scaling in advanced SOI processes. - Johannes Maximilian Kühn; Hideharu Amano; Oliver Bringmann 001; Wolfgang Rosenstiel (COOL Chips, 2015)

Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. - Johannes Maximilian Kühn; Dustin Peterson; Hideharu Amano; Oliver Bringmann 001; Wolfgang Rosenstiel (DATE, 2015)

Adaptive multi-layer techniques for increased system dependability. - Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes Maximilian Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich; Hongyan Zhang 004 (it Inf. Technol., 2015)

MuCCRA4-BB: A fine-grained body biasing capable DRP. - Johannes Maximilian Kühn; Akram Ben Ahmed; Hayate Okuhara; Hideharu Amano; Oliver Bringmann 001; Wolfgang Rosenstiel (COOL Chips, 2016)

Leveraging FDSOI through body bias domain partitioning and bias search. - Johannes Maximilian Kühn; Hideharu Amano; Oliver Bringmann 001; Wolfgang Rosenstiel (DAC, 2016)

Leveraging asymmetric body bias control for low power LSI design. - Hayate Okuhara; Akram Ben Ahmed; Johannes Maximilian Kühn; Hideharu Amano (COOL Chips, 2017)

Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. - Hayate Okuhara; Akram Ben Ahmed; Johannes Maximilian Kühn; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Building Scalable and Highly Efficient Accelerators Near the End of Conventional Scaling. - Johannes Maximilian Kühn (MCSoC, 2019)

Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators. - Tanvir Ahmed; Johannes Maximilian Kühn (FPGA, 2020)

A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping Method. - Tanvir Ahmed; Johannes Maximilian Kühn; Ken Namura (MCSoC, 2021)

MN-Core - A Highly Efficient and Scalable Approach to Deep Learning. - Ken Namura; Johannes Maximilian Kühn; Tohru Adachi; H. Imachi; H. Kaneko; T. Kato; Go Watanabe; Naoto Tanaka; S. Kashihara; Hiroshi Miyashita; Y. Tomonaga; Ryosuke Okuta; et al. (VLSI Circuits, 2021)