Organic Computing at the System on Chip Level. - Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf; Andreas Bernauer; Oliver Bringmann 001; Wolfgang Rosenstiel (VLSI-SoC, 2006)

Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. - Christopher Claus; Johannes Zeppenfeld; Florian Helmut Müller; Walter Stechele (DATE, 2007)

Power Estimation of Time Variant SoCs with TAPES. - Andreas Lankes; Thomas Wild; Johannes Zeppenfeld (DSD, 2007)

A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. - Christopher Claus; Florian Helmut Müller; Johannes Zeppenfeld; Walter Stechele (IPDPS, 2007)

System Level Simulation of Autonomic SoCs with TAPES. - Andreas Lankes; Thomas Wild; Johannes Zeppenfeld (ARCS, 2008)

Learning Classifier Tables for Autonomic Systems on Chip. - Johannes Zeppenfeld; Abdelmajid Bouajila; Walter Stechele; Andreas Herkersdorf (GI Jahrestagung (2), 2008)

Autonomic Workload Management for Multi-core Processor Systems. - Johannes Zeppenfeld; Andreas Herkersdorf (ARCS, 2010)

A rapid prototyping system for error-resilient multi-processor systems-on-chip. - Matthias May 001; Norbert Wehn; Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf; Daniel Ziener; Jürgen Teich (DATE, 2010)

Combining Software and Hardware LCS for Lightweight On-Chip Learning. - Andreas Bernauer; Johannes Zeppenfeld; Oliver Bringmann 001; Andreas Herkersdorf; Wolfgang Rosenstiel (DIPES/BICC, 2010)

Towards Scalability and Reliability of Autonomic Systems on Chip. - Johannes Zeppenfeld; Abdelmajid Bouajila; Andreas Herkersdorf; Walter Stechele (ISORC Workshops, 2010)

Combining Software and Hardware LCS for Lightweight On-chip Learning. - Andreas Bernauer; Johannes Zeppenfeld; Oliver Bringmann 001; Andreas Herkersdorf; Wolfgang Rosenstiel (Organic Computing, 2011)

Autonomic System on Chip Platform. - Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Bernauer; Oliver Bringmann 001; Wolfgang Rosenstiel; Andreas Herkersdorf (Organic Computing, 2011)

Applying ASoC to Multi-core Applications for Workload Management. - Johannes Zeppenfeld; Abdelmajid Bouajila; Walter Stechele; Andreas Bernauer; Oliver Bringmann 001; Wolfgang Rosenstiel; Andreas Herkersdorf (Organic Computing, 2011)

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. - Andreas Herkersdorf; Andreas Lankes; Michael Meitinger; Rainer Ohlendorf; Stefan Wallentowitz; Thomas Wild; Johannes Zeppenfeld (Multiprocessor System-on-Chip, 2011)

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. - Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf (DDECS, 2011)

Applying autonomic principles for workload management in multi-core systems on chip. - Johannes Zeppenfeld; Andreas Herkersdorf (ICAC, 2011)

A low-overhead monitoring ring interconnect for MPSoC parameter optimization. - Abdelmajid Bouajila; Abdallah Lakhtel; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf (DDECS, 2012)