A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. - Howard L. Kalter; Charles H. Stapper; John E. Barth Jr.; John DiLorenzo; Charles E. Drake; John A. Fifield; Gordon A. Kelley; Scott C. Lewis; Willem B. van der Hoeven; James A. Yankosky (IEEE J. Solid State Circuits, 1990)

High-speed on-chip ECC for synergistic fault-tolerance memory chips. - John A. Fifield; Charles H. Stapper (IEEE J. Solid State Circuits, 1991)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. - Darren Anand; Jim Covino; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Mark Jacunski; Jake Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2007)

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. - Mark Jacunski; Darren Anand; Robert Busch; John A. Fifield; Matthew Lanahan; Paul Lane; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Michael Roberge; Stephen Sliva (CICC, 2010)

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. - Eric Hunt-Schroeder; Darren Anand; John A. Fifield; Mark Jacunski; Michael Roberge; Dale E. Pontius; Kevin Batson; Toshiaki Kirihata (VLSI Circuits, 2018)