Design considerations for MRAM. - Thomas M. Maffitt; John K. DeBrosse; John A. Gabric; Earl T. Gow; Mark C. Lamorey; John S. Parenteau; Dennis R. Willmott; Mark A. Wood; William J. Gallagher (IBM J. Res. Dev., 2006)

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. - Harold Pilo; Vaidyanathan Ramadurai; Geordie Braceras; John A. Gabric; Steve Lamphier; Yue Tan (ISSCC, 2008)

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management. - Vinod Ramadurai; Harold Pilo; John Andersen; Geordie Braceras; John A. Gabric; Daniel Geise; Steve Lamphier; Yue Tan (IEEE J. Solid State Circuits, 2009)

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Frank Pavlik; Adnan Seferagic; Liang-Yu Chen; Shang-Bin Ko; Carl Radens (ISSCC, 2011)

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Carl Radens; Adnan Seferagic (IEEE J. Solid State Circuits, 2012)