Fault Diagnosis in an LSSD Environment. - Y. Arzoumanian; John A. Waicukauski (ITC, 1981)

An LSSD Pseudo Random Pattern Test System. - Franco Motika; John A. Waicukauski; Edward B. Eichelberger; Eric Lindbloom (ITC, 1983)

A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation. - John A. Waicukauski; Eric Lindbloom; Edward B. Eichelberger; Donato O. Forlenza; Tim McCarthy (ITC, 1985)

Transition Fault Simulation by Parallel Pattern Single Fault Propagation. - John A. Waicukauski; Eric Lindbloom; Vijay S. Iyengar; Barry K. Rosen (ITC, 1986)

Transition Fault Simulation. - John A. Waicukauski; Eric Lindbloom; Barry K. Rosen; Vijay S. Iyengar (IEEE Des. Test, 1987)

What is the Path to Fast Fault Simulation? - Miron Abramovici; Balaji Krishnamurthy; Rob Mathews; Bill Rogers; Michael Schulz; Sharad Seth; John A. Waicukauski (ITC, 1988)

Fault Detection Effectiveness of Weighted Random Patterns. - John A. Waicukauski; Eric Lindbloom (ITC, 1988)

Failure diagnosis of structured VLSI. - John A. Waicukauski; Eric Lindbloom (IEEE Des. Test, 1989)

A Method for Generating Weighted Random Test Patterns. - John A. Waicukauski; Eric Lindbloom; Edward B. Eichelberger; Orazio P. Forlenza (IBM J. Res. Dev., 1989)

ATPG for ultra-large structured designs. - John A. Waicukauski; Paul A. Shupe; David Giramma; Arshad Matin (ITC, 1990)

On computing the sizes of detected delay faults. - Vijay S. Iyengar; Barry K. Rosen; John A. Waicukauski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Universal Technique for Accelerating Simulation of Scan Test Patterns. - Bejoy G. Oomman; Wu-Tung Cheng; John A. Waicukauski (ITC, 1996)

Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. - Peter Wohl; John A. Waicukauski (ITC, 1996)

Two-Dimensional Test Data Decompressor for Multiple Scan Designs. - Nadime Zacharia; Janusz Rajski; Jerzy Tyszer; John A. Waicukauski (ITC, 1996)

Testing "untestable" faults in three-state circuits. - Peter Wohl; John A. Waicukauski; Matthew Graf (VTS, 1996)

A Unified Interface for Scan Test Generation Based on STIL. - Peter Wohl; John A. Waicukauski (ITC, 1997)

Using ATPG for clock rules checking in complex scan design. - Peter Wohl; John A. Waicukauski (VTS, 1997)

Extracting gate-level networks from simulation tables. - Peter Wohl; John A. Waicukauski (ITC, 1998)

Defining ATPG rules checking in STIL. - Peter Wohl; John A. Waicukauski (ITC, 1998)

Using Verilog simulation libraries for ATPG. - Peter Wohl; John A. Waicukauski (ITC, 1999)

Optimizing the flattened test-generation model for very large designs. - Peter Wohl; John A. Waicukauski (ITC, 2000)

Design of compactors for signature-analyzers in built-in self-test. - Peter Wohl; John A. Waicukauski; Thomas W. Williams (ITC, 2001)

Effective diagnostics through interval unloads in a BIST environment. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Gregory A. Maston (DAC, 2002)

Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. - Vishal Jain; John A. Waicukauski (ITC, 2002)

Efficient compression and application of deterministic patterns in a logic BIST architecture. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Minesh B. Amin (DAC, 2003)

X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Minesh B. Amin (ITC, 2003)

Scalable selector architecture for x-tolerant deterministic BIST. - Peter Wohl; John A. Waicukauski; Sanjay Patel (DAC, 2004)

Efficient compression of deterministic patterns into multiple PRPG seeds. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Francisco DaSilva; Thomas W. Williams; Rohit Kapur (ITC, 2005)

Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Cy Hay; Emil Gizdarski; Ben Mathew (VTS, 2005)

Fully X-tolerant combinational scan compression. - Peter Wohl; John A. Waicukauski; Sanjay Ramnath (ITC, 2007)

Minimizing the Impact of Scan Compression. - Peter Wohl; John A. Waicukauski; Rohit Kapur; Sanjay Ramnath; Emil Gizdarski; Thomas W. Williams; P. Jaini (VTS, 2007)

Automated Design and Insertion of Optimal One-Hot Bus Encoders. - Peter Wohl; John A. Waicukauski; Sanjay Patel (VTS, 2007)

Increasing Scan Compression by Using X-chains. - Peter Wohl; John A. Waicukauski; Frederic Neuveux (ITC, 2008)

Fully X-tolerant, very high scan compression. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Emil Gizdarski (DAC, 2010)

Highly efficient parallel ATPG based on shared memory. - X. Cai; Peter Wohl; John A. Waicukauski; Pramod Notiyath (ITC, 2010)

Increasing PRPG-based compression by delayed justification. - Peter Wohl; John A. Waicukauski; T. Finklea (ITC, 2010)

Hybrid selector for high-X scan compression. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Jonathon E. Colburn (ITC, 2012)

Enhancing testability by structured partial scan. - Peter Wohl; John A. Waicukauski; Jonathon E. Colburn (VTS, 2012)

Two-level compression through selective reseeding. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Gregory A. Maston; Nadir Achouri; Jonathon E. Colburn (ITC, 2013)

Improving test generation by use of majority gates. - Peter Wohl; John A. Waicukauski (VTS, 2013)

Achieving extreme scan compression for SoC Designs. - Peter Wohl; John A. Waicukauski; Jonathon E. Colburn; Milind Sonawane (ITC, 2014)

A New Paradigm for Synthesis of Linear Decompressors. - Emil Gizdarski; Peter Wohl; John A. Waicukauski (DAC, 2017)

XLBIST: X-Tolerant Logic BIST. - Peter Wohl; John A. Waicukauski; Gregory A. Maston; Jonathon E. Colburn (ITC, 2018)