Designing the M·CORETM M3 CPU Architecture. - Jeff Scott; Lea Hwang Lee; Ann Chin; John Arends; Bill Moyer (ICCD, 1999)

Instruction fetch energy reduction using loop caches for embedded applications with small tight loops. - Lea Hwang Lee; Bill Moyer; John Arends (ISLPED, 1999)

Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. - Lea Hwang Lee; Jeff Scott; Bill Moyer; John Arends (MICRO, 1999)

SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect. - Chia-Hsin Owen Chen; Sunghyun Park 002; Suvinay Subramanian; Tushar Krishna; Bhavya K. Daya; Woo-Cheol Kwon; Brett Wilkerson; John Arends; Anantha P. Chandrakasan; Li-Shiuan Peh (Hot Chips Symposium, 2014)

Latency Critical Operation in Network Processors. - Sourav Roy; Arvind Kaushik; Rajkumar Agrawal; Joseph Gergen; Wim Rouwet; John Arends (Hot Interconnects, 2019)

A High-Throughput Network Processor Architecture for Latency-Critical Applications. - Sourav Roy; Arvind Kaushik; Rajkumar Agrawal; Joseph Gergen; Wim Rouwet; John Arends (IEEE Micro, 2020)