Obtaining Structural Metrics of Z Specifications for Systems Development. - John Bainbridge; Robin W. Whitty; John Wordsworth (Z User Workshop, 1990)

A Heuristic Method for Generating Large Random Expressions. - John Bainbridge (Inf. Process. Lett., 1992)

Defining Testability Metrics Axiomatically. - John Bainbridge (Softw. Test. Verification Reliab., 1994)

Chain: A Delay-Insensitive Chip Area Interconnect. - John Bainbridge; Stephen B. Furber (IEEE Micro, 2002)

Adding Testability to an Asynchronous Interconnect for GALS SoC. - Aristides Efthymiou; John Bainbridge; Douglas A. Edwards (Asian Test Symposium, 2004)

Sparse distributed memory using N-of-M codes. - Stephen B. Furber; John Bainbridge; J. Mike Cumpstey; Steve Temple (Neural Networks, 2004)

Future Trends in SoC Interconnect. - Steve B. Furber; John Bainbridge (SoC, 2005)

Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. - Aristides Efthymiou; John Bainbridge; Douglas A. Edwards (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. - Andrew M. Scott; Mark E. Schuelein; Marly Roncken; Jin-Jer Hwan; John Bainbridge; John R. Mawer; David L. Jackson; Andrew Bardsley (ASYNC, 2007)

An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. - Luis A. Plana; John Bainbridge; Steve B. Furber; Sean Salisbury; Yebin Shi; Jian Wu (NOCS, 2008)

SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. - Luis A. Plana; David M. Clark; Simon Davidson; Steve B. Furber; Jim D. Garside; Eustace Painkras; Jeffrey Pepper; Steve Temple; John Bainbridge (ACM J. Emerg. Technol. Comput. Syst., 2011)