A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC. - Howard L. Kalter; Charles H. Stapper; John E. Barth Jr.; John DiLorenzo; Charles E. Drake; John A. Fifield; Gordon A. Kelley; Scott C. Lewis; Willem B. van der Hoeven; James A. Yankosky (IEEE J. Solid State Circuits, 1990)

Multipurpose DRAM architecture for optimal power, performance, and product flexibility. - Wayne F. Ellis; John E. Barth Jr.; Sri Divakaruni; Jeffrey H. Dreibelbis; Anatol Furman; Erik L. Hedberg; Hsing-San Lee; Thomas M. Maffitt; Christopher P. Miller; Charles H. Stapper; Howard L. Kalter (IBM J. Res. Dev., 1995)

Processor-based built-in self-test for embedded DRAM. - Jeffrey H. Dreibelbis; John Barth 001; Howard L. Kalter; Rex Kho (IEEE J. Solid State Circuits, 1998)

Embedded DRAM built in self test and methodology for test insertion. - Peter Jakobsen; Jeffrey H. Dreibelbis; Gary Pomichter; Darren Anand; John Barth 001; Michael R. Nelms; Jeffrey Leach; George M. Belansek (ITC, 2001)

Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. - John E. Barth Jr.; Jeffrey H. Dreibelbis; Eric A. Nelson; Darren Anand; Gary Pomichter; Peter Jakobsen; Michael R. Nelms; Jeffrey Leach; George M. Belansek (IBM J. Res. Dev., 2002)

A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. - Harold Pilo; Darren Anand; John Barth 001; Steve Burns 001; Phil Corson; Jim Covino; Steve Lamphier (IEEE J. Solid State Circuits, 2003)

Embedded DRAM: Technology platform for the Blue Gene/L chip. - Subramanian S. Iyer; John E. Barth Jr.; Paul C. Parries; James P. Norum; James P. Rice; Lyndon R. Logan; Dennis Hoyniak (IBM J. Res. Dev., 2005)

A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. - John E. Barth Jr.; Darren Anand; Steve Burns 001; Jeffrey H. Dreibelbis; John A. Fifield; Kevin W. Gorman; Michael R. Nelms; Erik Nelson; Adrian Paparelli; Gary Pomichter; Dale E. Pontius; Stephen Sliva (IEEE J. Solid State Circuits, 2005)

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. - Jente B. Kuang; Abraham Mathews; John Barth 001; Fadi H. Gebara; Tuyet Nguyen; Jeremy D. Schaub; Kevin J. Nowka; Gary D. Carpenter; Don Plass; Erik Nelson; Ivan Vo; William R. Reohr; et al. (ESSCIRC, 2008)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; William R. Reohr; Kavita Nair; Nianzheng Cao (ISSCC, 2010)

Three Dimensional integration - Considerations for memory applications. - Subramanian S. Iyer; Toshiaki Kirihata; John E. Barth Jr. (CICC, 2011)

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. - John Barth 001; Don Plass; Erik Nelson; Charlie Hwang; Gregory Fredeman; Michael A. Sperling; Abraham Mathews; Toshiaki Kirihata; William R. Reohr; Kavita Nair; Nianzheng Cao (IEEE J. Solid State Circuits, 2011)

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. - Balaji Jayaraman; Sneha Gupta; Yanli Zhang; Puneet Goyal; Herbert Ho; Rishikesh Krishnan; Sunfei Fang; Sungjae Lee; Douglas Daley; Kevin McStay; Bernhard Wunder; John Barth 001; et al. (ICICDT, 2012)

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. - John Barth 001; Don Plass; Adis Vehabovic; Rajiv V. Joshi; Rouwaida Kanj; Steven Burns 001; Todd Weaver (VLSIC, 2012)

A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. - Harold Pilo; John Barth 001; Kapil Dev Dwivedi; Peter Lee; Vikram Kumar; Prasanna Nalawar; Yogeshbhai Patel; Shailendra Sharad; Shakti Singh (ISSCC, 2025)