A generic system simulator with novel on-chip cache and throughput models for gigascale integration. - John C. Eble (1998)

A physical alpha-power law MOSFET model. - Keith A. Bowman; Blanca Austin; John C. Eble; Xinghai Tang; James D. Meindl (IEEE J. Solid State Circuits, 1999)

Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance. - Keith A. Bowman; Xinghai Tang; John C. Eble; James D. Menldl (IEEE J. Solid State Circuits, 2000)

A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI. - Wayne D. Dettloff; John C. Eble; Lei Luo 006; Pravin Kumar Venkatesan; Fred Heaton; Teva Stone; Barry Daly (ISSCC, 2010)

Power-efficient I/O design considerations for high-bandwidth applications. - John C. Eble; Scott Best; Brian S. Leibowitz; Lei Luo 006; Robert Palmer; John M. Wilson 002; Jared Zerbe; Amir Amirkhany; Nhat Nguyen (CICC, 2011)

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. - Jared Zerbe; Barry Daly; Lei Luo 006; Bill Stonecypher; Wayne D. Dettloff; John C. Eble; Teva Stone; Jihong Ren; Brian S. Leibowitz; Michael Bucher; Patrick Satarzadeh; Qi Lin; et al. (IEEE J. Solid State Circuits, 2011)

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on. - Dustin Dunwell; Anthony Chan Carusone; Jared Zerbe; Brian S. Leibowitz; Barry Daly; John C. Eble (CICC, 2012)

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. - Masum Hossain; Kambiz Kaviani; Barry Daly; Makarand Shirasgaonkar; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Brian Tsang; John C. Eble; Jared Zerbe (CICC, 2012)

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. - Kambiz Kaviani; Michael Bucher; Bruce Su; Barry Daly; Bill Stonecypher; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Pravin Kumar Venkatesan; Fred Heaton; Ravi T. Kollipara; Yi Lu; et al. (ISSCC, 2013)

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. - Masum Hossain; E-Hung Chen; Reza Navid; Brian S. Leibowitz; Chuen-Huei Adam Chou; Simon Li; Myeong-Jae Park; Jihong Ren; Barry Daly; Bruce Su; Makarand Shirasgaonkar; Fred Heaton; et al. (VLSIC, 2014)

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. - Michael Bucher; Ravi T. Kollipara; Bruce Su; Liji Gopalakrishnan; Kashinath Prabhu; Pravin Kumar Venkatesan; Kambiz Kaviani; Barry Daly; William F. Stonecypher; Wayne D. Dettloff; Teva Stone; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2014)

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface. - Masum Hossain; Farrukh Aquil; Pak Shing Chau; Brian Tsang; Phuong Le; Jason Wei; Teva Stone; Barry Daly; Chanh Tran; John C. Eble; Kurt Knorpp; Jared Zerbe (IEEE J. Solid State Circuits, 2014)

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. - Reza Navid; E-Hung Chen; Masum Hossain; Brian S. Leibowitz; Jihong Ren; Chuen-Huei Adam Chou; Barry Daly; Marko Aleksic; Bruce Su; Simon Li; Makarand Shirasgaonkar; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2015)