A chip set microarchitecture for a high-performance VAX implementation. - John F. Brown III; Richard L. Sites (MICRO, 1984)

Design verification of a VLSI VAX microcomputer. - Sridhar Samudrala; Charles Lo; John F. Brown III; Richard E. Calcagni (MICRO, 1984)

NVAX and NVAX + Single-Chip CMOS VAX Microprocessors. - Debra Bernstein; John F. Brown III; Rebecca L. Stamm; G. Michael Uhler (ICCD, 1992)

The NVAX and NVAX+ High-Performance VAX Microprocessor. - G. Michael Uhler; Debra Bernstein; Larry L. Biro; John F. Brown III; John H. Edmondson; Jeffrey D. Pickholtz; Rebecca L. Stamm (Digit. Tech. J., 1992)

A 100-MHz macropipelined VAX microprocessor. - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)

On-Chip Interconnection Architecture of the Tile Processor. - David Wentzlaff; Patrick Griffin; Henry Hoffmann; Liewei Bao; Bruce Edwards; Carl Ramey; Matthew Mattina; Chyi-Chang Miao; John F. Brown III; Anant Agarwal (IEEE Micro, 2007)

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect. - Shane Bell; Bruce Edwards; John Amann; Rich Conlin; Kevin Joyce; Vince Leung; John MacKay; Mike Reif; Liewei Bao; John F. Brown III; Matthew Mattina; Chyi-Chang Miao; et al. (ISSCC, 2008)