A 155-MHz clock recovery delay- and phase-locked loop. - Thomas H. Lee; John F. Bulzacchelli (IEEE J. Solid State Circuits, 1992)

Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. - John F. Bulzacchelli; Hae-Seung Lee; James A. Misewich; Mark B. Ketchen (IEEE J. Solid State Circuits, 2002)

A superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio. - John F. Bulzacchelli (2003)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. - Matt Park; John F. Bulzacchelli; Michael P. Beakes; Daniel J. Friedman (ISSCC, 2007)

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. - Azita Emami-Neyestanak; Aida Varzaghani; John F. Bulzacchelli; Alexander V. Rylyakov; Chih-Kong Ken Yang; Daniel J. Friedman (IEEE J. Solid State Circuits, 2007)

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. - John F. Bulzacchelli; Timothy O. Dickson; Zeynep Toprak Deniz; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS. - Yong Liu 023; Byungsub Kim; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (ISSCC, 2009)

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. - Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Jean-Olivier Plouchart; John F. Bulzacchelli; Zeynep Toprak Deniz; Daniel J. Friedman (ISSCC, 2009)

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. - Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. - Byungsub Kim; Yong Liu 023; Timothy O. Dickson; John F. Bulzacchelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2009)

A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (ISSCC, 2012)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

Root cause identification of an hard-to-find on-chip power supply coupling fail. - Franco Stellari; Thomas Cowell; Peilin Song; Michael Sorna; Zeynep Toprak Deniz; John F. Bulzacchelli; Nandita A. Mitra (ITC, 2012)

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. - Ankur Agrawal; John F. Bulzacchelli; Timothy O. Dickson; Yong Liu 023; José A. Tierno; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. - John F. Bulzacchelli; Zeynep Toprak Deniz; Todd M. Rasmus; Joseph A. Iadanza; William L. Bucossi; Seongwon Kim; Rafael Blanco; Carrie E. Cox; Mohak Chhabra; Christopher D. LeBlanc; Christian L. Trudeau; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

Design techniques for CMOS backplane transceivers approaching 30-Gb/s data rates. - John F. Bulzacchelli (CICC, 2013)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (ISSCC, 2015)

A WDM-Compatible 4 × 32-Gb/s CMOS-driven electro-absorption modulator array. - Benjamin G. Lee; Renato Rimolo-Donadio; Alexander V. Rylyakov; Jonathan E. Proesel; John F. Bulzacchelli; Christian W. Baks; Mounir Meghelli; Clint L. Schow; Anand Ramaswamy; Jonathan E. Roth; Jae-Hyuk Shin; Brian R. Koch; et al. (OFC, 2015)

A 25 Gb/s burst-mode receiver for low latency photonic switch networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Clint Schow; Mounir Meghelli (OFC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (IEEE J. Solid State Circuits, 2015)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; Timothy E. Diemoz; John F. Bulzacchelli; Zeynep Toprak Deniz (CICC, 2019)

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (ISSCC, 2019)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; John F. Bulzacchelli; Zeynep Toprak Deniz; Timothy E. Diemoz (IEEE J. Solid State Circuits, 2020)

A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. - Kevin Tien; Ken Inoue; Scott Lekuch; David J. Frank; Sudipto Chakraborty; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; et al. (DATE, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Thomas Fox; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; et al. (ISSCC, 2022)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. - Sudipto Chakraborty; David J. Frank; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Devin Underwood; Daniel Ramirez; Dereje Yilma; et al. (IEEE J. Solid State Circuits, 2022)

Low power cryogenic RF ASICs for quantum computing. - David J. Frank; Sudipto Chakraborty; Kevin Tien; Pat Rosno; Mark Yeck; Joseph A. Glick; Raphael Robertazzi; Ray Richetta; John F. Bulzacchelli; Daniel Ramirez; Dereje Yilma; Andrew Davies; et al. (CICC, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)

Cryogenic CMOS Circuits for Future Scaled Quantum Computing Systems: Challenges and Solutions. - Bodhisatwa Sadhu; Kevin Tien; Sudipto Chakraborty; David J. Frank; Pat Rosno; Daniel Moertl; Mark Yeck; John F. Bulzacchelli; Daniil Frolov; Devin Underwood; Ken Inoue; Christian W. Baks; et al. (CICC, 2025)