Low-Cost Testing of High-Density Logic Components. - Robert W. Bassett; Barry J. Butkus; Stephen L. Dingle; Marc R. Faucher; Pamela S. Gillis; Jeannie H. Panner; John G. Petrovick; Donald L. Wheater (IEEE Des. Test Comput., 1990)

A pseudo-hierarchical methodology for high performance microprocessor design. - A. Bertolet; K. Carpenter; Keith M. Carrig; Albert M. Chu; A. Dean; Frank D. Ferraiolo; Stephan Kenyon; D. Phan; John G. Petrovick; G. Rodgers; D. Willmott; T. Bairley; et al. (ISPD, 1997)

A Clock Methodology for High-Performance Microprocessors. - Keith M. Carrig; Albert M. Chu; Frank D. Ferraiolo; John G. Petrovick; P. Andrew Scott; Richard J. Weiss (J. VLSI Signal Process., 1997)

A clock distribution network for microprocessors. - Phillip J. Restle; Timothy G. McNamara; David A. Webber; Peter J. Camporese; Kwok F. Eng; Keith A. Jenkins; David H. Allen; Michael J. Rohn; Michael P. Quaranta; David W. Boerstler; Charles J. Alpert; Craig A. Carter; et al. (IEEE J. Solid State Circuits, 2001)

The circuit and physical design of the POWER4 microprocessor. - James D. Warnock; John M. Keaty; John G. Petrovick; Joachim G. Clabes; Charles J. Kircher; Byron Krauter; Phillip J. Restle; Brian A. Zoric; Carl J. Anderson (IBM J. Res. Dev., 2002)

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. - Dac C. Pham; Hans-Werner Anderson; Erwin Behnen; Mark Bolliger; Sanjay Gupta; H. Peter Hofstee; Paul E. Harvey; Charles R. Johns; James A. Kahle; Atsushi Kameyama; John M. Keaty; Bob Le; et al. (ASP-DAC, 2006)