An 800-MHz embedded DRAM with a concurrent refresh mode. - Toshiaki Kirihata; Paul C. Parries; David R. Hanson; Hoki Kim; John Golz; Gregory Fredeman; Raj Rajeevakumar; John Griesemer; Norman Robson; Alberto Cestero; Babar A. Khan; Geng Wang; et al. (IEEE J. Solid State Circuits, 2005)

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (ISSCC, 2007)

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. - John Barth 001; William R. Reohr; Paul C. Parries; Gregory Fredeman; John Golz; Stanley Schuster; Richard E. Matick; Hillery C. Hunter; Charles Tanner; Joseph Harig; Hoki Kim; Babar A. Khan; et al. (IEEE J. Solid State Circuits, 2008)

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. - Janakiraman Viraraghavan; Derek Leu; Balaji Jayaraman; Alberto Cestero; Robert Kilker; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; et al. (VLSI Circuits, 2016)

OfftargetFinder: a web tool for species-specific RNAi design. - Robert T. Good; Temi Varghese; John Golz; Derek A. Russell; Alexie Papanicolaou; Owain Edwards; Charles Robin (Bioinform., 2016)

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias. - Toshiaki Kirihata; John Golz; Matthew R. Wordeman; Pooja Batra; Gary W. Maier; Norman Robson; Troy L. Graves-abe; Daniel Berger; Subramanian S. Iyer (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. - Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; et al. (IEEE J. Solid State Circuits, 2018)