The NVAX and NVAX+ High-Performance VAX Microprocessor. - G. Michael Uhler; Debra Bernstein; Larry L. Biro; John F. Brown III; John H. Edmondson; Jeffrey D. Pickholtz; Rebecca L. Stamm (Digit. Tech. J., 1992)

A 100-MHz macropipelined VAX microprocessor. - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)

Testability Strategy of the ALPHA AXP 21164 Microprocessor. - Dilip K. Bhavsar; John H. Edmondson (ITC, 1994)

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU - William J. Bowhill; Shane L. Bell; Bradley J. Benschneider; Andrew J. Black; Sharon M. Britton; Ruben W. Castelino; Dale R. Donchin; John H. Edmondson; Harry R. Fair III; Paul E. Gronowski; Anil K. Jain 003; Patricia L. Kroesen; et al. (Digit. Tech. J., 1995)

Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor - John H. Edmondson; Paul I. Rubinfeld; Peter J. Bannon; Bradley J. Benschneider; Debra Bernstein; Ruben W. Castelino; Elizabeth M. Cooper; Daniel E. Dever; Dale R. Donchin; Timothy C. Fischer; Anil K. Jain 003; Shekhar Mehta; et al. (Digit. Tech. J., 1995)

Superscalar instruction execution in the 21164 Alpha microprocessor. - John H. Edmondson; Paul I. Rubinfeld; Ronald P. Preston; Vidya Rajagopalan (IEEE Micro, 1995)

Alpha 21164 Testability Strategy. - Dilip K. Bhavsar; John H. Edmondson (IEEE Des. Test Comput., 1997)

Performance Simulation of an Alpha Microprocessor. - Matt Reilly; John H. Edmondson (Computer, 1998)

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Hiok-Tiaq Ng; Ming-Ju Edward Lee; Ramin Farjad-Rad; Ramesh Senthinathan; William J. Dally; Anhtuyet Nguyen; Rohit Rathi; Trey Greer; John Poulton; John H. Edmondson; James Tran (CICC, 2003)

CMOS High-Speed I/Os - Present and Future. - Ming-Ju Edward Lee; William J. Dally; Ramin Farjad-Rad; Hiok-Tiaq Ng; Ramesh Senthinathan; John H. Edmondson; John W. Poulton (ICCD, 2003)

A second-order semidigital clock recovery circuit based on injection locking. - Hiok-Tiaq Ng; Ramin Farjad-Rad; Ming-Ju Edward Lee; William J. Dally; Trey Greer; John Poulton; John H. Edmondson; Rohit Rathi; Ramesh Senthinathan (IEEE J. Solid State Circuits, 2003)

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. - Ramin Farjad-Rad; Anhtuyet Nguyen; James Tran; Trey Greer; John Poulton; William J. Dally; John H. Edmondson; Ramesh Senthinathan; Rohit Rathi; Ming-Ju Edward Lee; Hiok-Tiaq Ng (IEEE J. Solid State Circuits, 2004)