A 6-ns cycle 256-kb cache memory and memory management unit. - Raymond A. Heald; John Holst (IEEE J. Solid State Circuits, 1993)

Circuit techniques in a 266-MHz MMX-enabled processor. - Don Draper; Matt Crowley; John Holst; Greg Favor; Albrecht Schoy; Jeff Trull; Amos Ben-Meir; Rajesh Khanna; Dennis Wendell; Ravi Krishna; Joe Nolan; Dhiraj Mallick; et al. (IEEE J. Solid State Circuits, 1997)