The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. - Don Weiss; John J. Wuu; Victor Chin (IEEE J. Solid State Circuits, 2002)

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. - Anant Singh; Michael Ciraula; Don Weiss; John J. Wuu; Philippe Bauser; Paul de Champs; Hamid Daghighian; David E. Fisch; Philippe Graber; Michel Bron (ISSCC, 2009)

An 8MB level-3 cache in 32nm SOI with column-select aliasing. - Don Weiss; Michael Dreesen; Michael Ciraula; Carson Henrion; Chris Helt; Ryan Freese; Tommy Miles; Anita Karegar; Russell Schreiber; Bryan Schneller; John J. Wuu (ISSCC, 2011)

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. - John J. Wuu; Rahul Agarwal; Michael Ciraula; Carl Dietz; Brett Johnson; Dave Johnson 002; Russell Schreiber; Raja Swaminathan; Will Walker; Samuel Naffziger (ISSCC, 2022)

11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems. - Alan Smith; Eric Chapman; Chintan Patel; Raja Swaminathan; John J. Wuu; Tyrone Huang; Wonjun Jung; Alexander Kaganov; Hugh McIntyre; Ramon Mangaser (ISSCC, 2024)

AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. - Alan Smith 003; Gabriel H. Loh; John J. Wuu; Samuel Naffziger; Tyrone Huang; Hugh McIntyre; Ramon Mangaser; Wonjun Jung; Raja Swaminathan (VLSI Technology and Circuits, 2024)

Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator. - Alan Smith 003; Gabriel H. Loh; Samuel Naffziger; John J. Wuu; Nathan Kalyanasundharam; Eric Chapman; Raja Swaminathan; Tyrone Huang; Wonjun Jung; Alexander Kaganov; Hugh McIntyre; Ramon Mangaser (IEEE Micro, 2025)