BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. - John Jose; J. Shiva Shankar; K. V. Mahathi; Damarla Kranthi Kumar; Madhu Mutyam (NoCArc@MICRO, 2011)

TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. - John Jose; K. V. Mahathi; J. Shiva Shankar; Madhu Mutyam (ICCAD, 2012)

DeBAR: deflection based adaptive router with minimal buffering. - John Jose; Bhawna Nayak; Damarla Kranthi Kumar; Madhu Mutyam (DATE, 2013)

SLIDER: Smart Late Injection DEflection Router for mesh NoCs. - Bhawna Nayak; John Jose; Madhu Mutyam (ICCD, 2013)

Minimally buffered single-cycle deflection router. - Gnaneswara Rao Jonna; John Jose; Rachana Radhakrishnan; Madhu Mutyam (DATE, 2014)

WeDBless: weighted deflection bufferless router for mesh NoCs. - Simi Zerine Sleeba; John Jose; Maniyelil Govindankutty Mini (ACM Great Lakes Symposium on VLSI, 2014)

Study and analysis of various task scheduling algorithms in the cloud computing environment. - Teena Mathew; K. Chandra Sekaran; John Jose (ICACCI, 2014)

An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers. - John Jose; Bivil M. Jacob; Hashim P. Kamal (NoCArc@MICRO, 2014)

Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. - John Jose; Madhu Mutyam (ACM Trans. Design Autom. Electr. Syst., 2014)

Dynamic migratory selection strategy for adaptive routing in mesh NoCs. - John Jose; Joe Augustine; Sijin Sebastian (VLSI-SoC, 2015)

Smart Port Allocation for Adaptive NoC Routers. - Reenu James; John Jose; Jobin K. Antony (VLSID, 2015)

Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs. - N. S. Aswathy; R. S. Reshma Raj; Abhijit Das 002; John Jose; V. R. Josna (VDAT, 2017)

Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique. - R. S. Reshma Raj; Abhijit Das 002; John Jose (VLSI-SoC, 2017)

Impact of deflection history based priority on adaptive deflection router for mesh NoCs. - Elizabeth Isaac; M. Rajasekhara Babu; John Jose (Electron. Gov. an Int. J., 2017)

Approximate Wireless Networks-on-Chip. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (DCIS, 2018)

ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (ISED, 2018)

Improving energy consumption of NoC based architectures through approximate communication. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (MECO, 2018)

Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. - Abhijit Das 002; Sarath Babu 003; John Jose; Sangeetha Jose; Maurizio Palesi (NOCS, 2018)

Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes. - K. S. Midhula; Sarath Babu 003; John Jose; Sangeetha Jose (VDAT, 2018)

Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip. - Akshay B. P.; Ganesh K. M.; Thippeswamy D. R.; Vishnu S. Bhat; Anitha Vijayakumar; Ananda Y. R.; John Jose (VDAT, 2018)

Source Hotspot Management in a Mesh Network on Chip. - Ajay S; Satya Sai Krishna Mohan G; Shashank S Rao; Sujay B Shaunak; Krutthika H. K; Ananda Y. R.; John Jose (VDAT, 2018)

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. - Simi Zerine Sleeba; John Jose; Maurizio Palesi; Rekha K. James; Maniyelil Govindankutty Mini (VLSI-SoC, 2018)

An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs. - John Jose; Abhijit Das 002 (VLSID, 2018)

Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips. - Simi Zerine Sleeba; John Jose; Maniyelil Govindankutty Mini (IET Comput. Digit. Tech., 2018)

Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (IoTSMS, 2019)

Asymmetric routing in 3D NoC using interleaved edge routers. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (NoCArc@MICRO, 2019)

Analyzing networks-on-chip based deep neural networks. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose (NOCS, 2019)

DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip. - Rose George Kunthara; K. Neethu; Rekha K. James; Simi Zerine Sleeba; John Jose (TENCON, 2019)

2L-2D Routing for Buffered Mesh Network-on-Chip. - Rose George Kunthara; K. Neethu; Rekha K. James; Simi Zerine Sleeba; Tripti S. Warrier; John Jose (VDAT, 2019)

Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. - Dipika Deb; John Jose; Maurizio Palesi (VLSID, 2019)

ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. - Dipika Deb; John Jose; Maurizio Palesi (IET Comput. Digit. Tech., 2019)

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. - Dipika Deb; John Jose; Shirshendu Das; Hemangee K. Kapoor (J. Parallel Distributed Comput., 2019)

Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. - Joe Augustine; Kanakagiri Raghavendra; John Jose; Madhu Mutyam (ICCD, 2020)

Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers. - Abhijit Das 002; Abhishek Kumar; John Jose (ICCD, 2020)

Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. - Giuseppe Ascia; Vincenzo Catania; John Jose; Salvatore Monteleone; Maurizio Palesi; Davide Patti (IPDPS Workshops, 2020)

Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (ISVLSI, 2020)

SECTAR: Secure NoC using Trojan Aware Routing. - Manju Rajan; Abhijit Das 002; John Jose; Prabhat Mishra 001 (NOCS, 2020)

Exploiting Data Resilience in Wireless Network-on-chip Architectures. - Giuseppe Ascia; Vincenzo Catania; Salvatore Monteleone; Maurizio Palesi; Davide Patti; John Jose; Valerio Mario Salerno (ACM J. Emerg. Technol. Comput. Syst., 2020)

Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning. - S. Sivakumar; T. M. Abdul Khader; John Jose (ACM Great Lakes Symposium on VLSI, 2021)

Dead flit attack on NoC by hardware trojan and its impact analysis. - Mohammad Humam Khan; Ruchika Gupta; John Jose; Sukumar Nandi (NoCArc@MICRO, 2021)

Packet header attack by hardware trojan in NoC based TCMP and its impact analysis. - Vedika J. Kulkarni; Manju Rajan; Ruchika Gupta; John Jose; Sukumar Nandi (NOCS, 2021)

Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems. - Abhijit Das 002; John Jose; Prabhat Mishra 001 (CoRR, 2021)

Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (Nano Commun. Networks, 2021)

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (IEEE Trans. Computers, 2021)

COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. - Dipika Deb; John Jose; Maurizio Palesi (ACM Trans. Design Autom. Electr. Syst., 2021)

Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems. - Abhijit Das 002; John Jose; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging. - Ruchika Gupta; Vedika J. Kulkarni; John Jose; Sukumar Nandi (ACM Great Lakes Symposium on VLSI, 2022)

DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (ACM Great Lakes Symposium on VLSI, 2022)

Design and Evaluation of a Rack-Scale Disaggregated Memory Architecture For Data Centers. - Amit Puri; John Jose; Tamarapalli Venkatesh (HPCC/DSS/SmartCity/DependSys, 2022)

Designing Data-Aware Network-on-Chip for Performance. - Abhijit Das 002; John Jose (ISVLSI, 2022)

LOKI: A Hardware Trojan Affecting Multiple Components of an SoC. - Manju Rajan; Abhijit Das 002; John Jose (ISVLSI, 2022)

Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks. - Mohammad Humam Khan; Ruchika Gupta; Vedika J. Kulkarni; John Jose; Sukumar Nandi (VLSI-SoC, 2022)

ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. - Yogesh Kumar 002; S. Sivakumar; John Jose (VLSI-SoC, 2022)

RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. - Akshay Sarman; Alwin Shaju; Rose George Kunthara; K. Neethu; Rekha K. James; John Jose (VLSI-SoC, 2022)

Revising NoC in Future Multicore-Based Consumer Electronics for Performance. - Abhijit Das 002; Abhishek Kumar; John Jose; Maurizio Palesi (IEEE Consumer Electron. Mag., 2022)

Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures. - Sudeep Pasricha; John Jose; Sujay Deb (IEEE Des. Test, 2022)

FlitZip: Effective Packet Compression for NoC in MultiProcessor System-on-Chip. - Dipika Deb; Rohith M. K.; John Jose (IEEE Trans. Parallel Distributed Syst., 2022)

Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. - Maurizio Palesi; Enrico Russo 002; Abhijit Das 002; John Jose (IPDPS Workshops, 2023)

Exploring Trustable Paths in Network-on-Chip for Low-Slack Packets. - Syam Sankar; Lissiyas Antony; Ruchika Gupta; John Jose; Sukumar Nandi (ISOCC, 2023)

PortBlocker: Detection and Mitigation of Hardware Trojan through Re-routing and Bypassing. - Sachin Bagga; Ruchika Gupta; John Jose (MCSoC, 2023)

Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip. - V. R. Josna; Rose George Kunthara; Rekha K. James; John Jose (MCSoC, 2023)

Understanding the Performance Impact of Queue-Based Resource Allocation in Scalable Disaggregated Memory Systems. - Amit Puri; Abir Banerjee; John Jose; Tamarapalli Venkatesh (MCSoC, 2023)

Enhancing Anonymity in NoC Communication to Counter Traffic Profiling by Hardware Trojans. - Syam Sankar; John Jose; Ruchika Gupta; Sukumar Nandi (MCSoC, 2023)

A Practical Approach For Workload-Aware Data Movement in Disaggregated Memory Systems. - Amit Puri; Kartheek Bellamkonda; Kailash Narreddy; John Jose; Tamarapalli Venkatesh (SBAC-PAD, 2023)

Strengthening NoC Security: Leveraging Hybrid Encryption for Data Packet Protection. - Thejaswini P; Sahana A. R.; Shankar Singh C.; John Jose (TENCON, 2023)

DRackSim: Simulator for Rack-scale Memory Disaggregation. - Amit Puri; John Jose; Tamarapalli Venkatesh; Vijaykrishnan Narayanan (CoRR, 2023)

Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks. - Rose George Kunthara; V. R. Josna; K. Neethu; Rekha K. James; John Jose (SN Comput. Sci., 2023)

ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs. - Dipika Deb; John Jose (ACM Trans. Embed. Comput. Syst., 2023)

Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip. - Manju Rajan; Mayank Choksey; John Jose (J. Syst. Archit., 2023)

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC. - S. Sivakumar; John Jose (ACM Trans. Design Autom. Electr. Syst., 2023)

ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training. - K. Neethu; K. C. Sharin Shahana; Rekha K. James; John Jose; Sumit K. Mandal (IEEE Des. Test, 2023)

Handling Packet Blocking Attack in NoC Using Traffic Snooping. - Manju Rajan; Arya Phadke; Syam Sankar; John Jose (COINS, 2024)

COPAR: Coordinated Packet Rerouting Attacks in NoC. - Sreehari Udayakumar Saritha; Manju Rajan; John Jose (ISED, 2024)

DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems. - Amit Puri; Kartheek Bellamkonda; Kailash Narreddy; John Jose; Venkatesh Tamarapalli; Vijaykrishnan Narayanan (SIGSIM-PADS, 2024)

TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans. - Syam Sankar; Ruchika Gupta; John Jose; Sukumar Nandi (ACM Trans. Design Autom. Electr. Syst., 2024)

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers. - S. Sivakumar; John Jose; Vijaykrishnan Narayanan (ACM Trans. Design Autom. Electr. Syst., 2024)

Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects. - Syam Sankar; Ruchika Gupta; John Jose; Sukumar Nandi (IEEE Embed. Syst. Lett., 2024)

Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip. - Rose George Kunthara; Rekha K. James; Simi Zerine Sleeba; John Jose (J. Circuits Syst. Comput., 2024)

Case Study: AI-Driven Log Extraction and Trace Outlier Detection for Efficient Post-Silicon Validation. - Kowshic A. Akash; Tobias Wulf; Torsten Valentin; Alexander Geist; Ulf Kulau; John Jose; Sohan Lal (LATS, 2025)

CosMoS: Architectural Support for Cost-Effective Data Movement in a Disaggregated Memory Systems. - Amit Puri; John Jose; Venkatesh Tamarapalli (ACM J. Emerg. Technol. Comput. Syst., 2025)

Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks. - Manju Rajan; Abhijit Das 002; John Jose (ACM Trans. Design Autom. Electr. Syst., 2025)