The evolution of IBM CMOS DRAM technology. - Eric Adler; John K. DeBrosse; Stephen F. Geissler; Steven J. Holmes; Mark D. Jaffe; Jeffrey B. Johnson; Charles W. Koburger III; Jerome B. Lasky; Brian Lloyd; Glen L. Miles; James S. Nakos; Wendell P. Noble Jr.; et al. (IBM J. Res. Dev., 1995)

Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

Flexible test mode approach for 256-Mb DRAM. - Toshiaki Kirihata; Hing Wong; John K. DeBrosse; Yohji Watanabe; Takahiko Hara; Munehiro Yoshida; Matthew R. Wordeman; Shuso Fujii; Yoshiaki Asao; Bo Krsnik (IEEE J. Solid State Circuits, 1997)

A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. - Toshiaki Kirihata; Martin Gall; Kohji Hosokawa; Jean-Marc Dortu; Hing Wong; Peter Pfefferl; Brian L. Ji; Oliver Weinfurtner; John K. DeBrosse; Hartmud Terletzki; Manfred Selz; Wayne Ellis; et al. (IEEE J. Solid State Circuits, 1998)

A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs. - Heinz Hoenigschmid; Alexander Frey; John K. DeBrosse; Toshiaki Kirihata; Gerhard Mueller; Daniel W. Storaska; Gabriel Daniel; Gerd Frankowsky; Kevin P. Guay; David R. Hanson; Louis Lu-Chen Hsu; Brian Ji; et al. (IEEE J. Solid State Circuits, 2000)

Challenges and future directions for the scaling of dynamic random-access memory (DRAM). - Jack A. Mandelman; Robert H. Dennard; Gary B. Bronner; John K. DeBrosse; Rama Divakaruni; Yujun Li; Carl J. Raden (IBM J. Res. Dev., 2002)

A high-speed 128-kb MRAM core for future universal memory applications. - John K. DeBrosse; Dietmar Gogl; Alexander Bette; Heinz Hoenigschmid; Raphael Robertazzi; Christian Arndt; Daniel Braun 011; D. Casarotto; Robert Havreluk; Stefan Lammers; Werner Obermaier; William R. Reohr; et al. (IEEE J. Solid State Circuits, 2004)

A 16-Mb MRAM featuring bootstrapped write drivers. - Dietmar Gogl; Christian Arndt; John C. Barwin; Alexander Bette; John K. DeBrosse; Earl T. Gow; Heinz Hoenigschmid; Stefan Lammers; Mark C. Lamorey; Yu Lu; Tom Maffitt; Kim Maloney; et al. (IEEE J. Solid State Circuits, 2005)

Design considerations for MRAM. - Thomas M. Maffitt; John K. DeBrosse; John A. Gabric; Earl T. Gow; Mark C. Lamorey; John S. Parenteau; Dennis R. Willmott; Mark A. Wood; William J. Gallagher (IBM J. Res. Dev., 2006)

A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing. - John K. DeBrosse; Thomas M. Maffitt; Yutaka Nakamura; Guenole Jan; Po-Kang Wang (CICC, 2015)