Width Quantization Aware FinFET Circuit Design. - Jie Gu 003; John Keane 001; Sachin S. Sapatnekar; Chris H. Kim (CICC, 2006)

Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing. - John Keane 001; Hanyong Eom; Tony Tae-Hyoung Kim; Sachin S. Sapatnekar; Chris H. Kim (DAC, 2006)

Modeling and analysis of leakage induced damping effect in low voltage LSIs. - Jie Gu 003; John Keane 001; Chris H. Kim (ISLPED, 2006)

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISSCC, 2007)

Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design. - Tony Tae-Hyoung Kim; John Keane 001; Hanyong Eom; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Circuit techniques for ultra-low power subthreshold SRAMs. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (ISCAS, 2008)

A multi-story power delivery technique for 3D integrated circuits. - Pulkit Jain; Tony Tae-Hyoung Kim; John Keane 001; Chris H. Kim (ISLPED, 2008)

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. - Tony Tae-Hyoung Kim; Jason Liu 004; John Keane 001; Chris H. Kim (IEEE J. Solid State Circuits, 2008)

Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. - Jie Gu 003; John Keane 001; Sachin S. Sapatnekar; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. - John Keane 001; Hanyong Eom; Tony Tae-Hyoung Kim; Sachin S. Sapatnekar; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. - Jie Gu 003; Hanyong Eom; John Keane 001; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. - Jie Gu 003; John Keane 001; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)

An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. - John Keane 001; Xiaofei Wang; Devin Persaud; Chris H. Kim (IEEE J. Solid State Circuits, 2010)

On-chip reliability monitors for measuring circuit degradation. - John Keane 001; Tony Tae-Hyoung Kim; Xiaofei Wang; Chris H. Kim (Microelectron. Reliab., 2010)

An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation. - John Keane 001; Tony Tae-Hyoung Kim; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization. - John Keane 001; Wei Zhang 032; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. - John Keane 001; Shrinivas Venkatraman; Paulo F. Butzen; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2011)

An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. - Pulkit Jain; John Keane 001; Chris H. Kim (ESSDERC, 2012)

Process and Reliability Sensors for Nanoscale CMOS. - John Keane 001; Chris H. Kim; Qunzeng Liu; Sachin S. Sapatnekar (IEEE Des. Test Comput., 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage. - Won Ho Choi; Saroj Satapathy; John Keane 001; Chris H. Kim (CICC, 2014)

Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. - Xiaofei Wang; John Keane 001; Tony Tae-Hyoung Kim; Pulkit Jain; Qianying Tang; Chris H. Kim (IEEE Micro, 2014)

17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2015)

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. - Kyung-Hoae Koo; Liqiong Wei; John Keane 001; Uddalak Bhattacharya; Eric A. Karl; Kevin Zhang 001 (VLSIC, 2015)

17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. - John Keane 001; Jaydeep Kulkarni; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (ISSCC, 2016)

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. - Eric Karl; Zheng Guo; James W. Conary; Jeffrey L. Miller; Yong-Gee Ng; Satyanand Nalam; Daeyeon Kim; John Keane 001; Xiaofei Wang; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2016)

5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. - Jaydeep P. Kulkarni; John Keane 001; Kyung-Hoae Koo; Satyanand Nalam; Zheng Guo; Eric Karl; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2017)