John Lee

Affiliations:
  • University of California at Los Angeles, CA, USA


According to our database1, John Lee authored at least 10 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Discrete sizing for leakage power optimization in physical design: A comparative study.
ACM Trans. Design Autom. Electr. Syst., 2012

ECO cost measurement and incremental gate sizing for late process changes.
ACM Trans. Design Autom. Electr. Syst., 2012

Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment.
Found. Trends Electron. Des. Autom., 2012

Parametric Hierarchy Recovery in Layout Extracted Netlists.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Impact of range and precision in technology on cell-based design.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
A unified optimization framework for simultaneous gate sizing and placement under density constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Evaluating Statistical Power Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Incremental gate sizing for late process changes.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
On the futility of statistical power optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Robust gate sizing via mean excess delay minimization.
Proceedings of the 2008 International Symposium on Physical Design, 2008


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